Advanced techniques for GA-based sequential ATPGs

Corno, Fulvio; Prinetto, P.; Rebaudengo, Maurizio; Reorda, M. Sonza; Mosca, Roberto

doi:10.1109/edtc.1996.494328

Cited by 37 publications

(13 citation statements)

References 6 publications

(11 reference statements)

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“…Another class of gate-level approaches, called simulation-based approaches [Seshu and Freeman 1962;Cheng and Agrawal 1989;Saab et al 1992;Prinetto et al 1994;Nitta et al 1985;Srinivas and Patnaik 1993;Pomeranz and Reddy 1995;Corno et al 1996], is enhanced from a logic simulator or a fault simulator. These approaches are combinations of simulation, and cost function guidance.…”

Section: Simulation-based Approachesmentioning

confidence: 99%

Gate-level test generation for sequential circuits

Cheng

1996

ACM Trans. Des. Autom. Electron. Syst.

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Section: Simulation-based Approachesmentioning

confidence: 99%

Gate-level test generation for sequential circuits

Cheng

1996

ACM Trans. Des. Autom. Electron. Syst.

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“…Evolutionary Computation techniques, such as Genetic Algorithms (GAs) [8], have been proposed in the last years as a valuable solution to improve the performance of simulationbased ATPGs for sequential circuits [6] [14] [15] [16] [17]. In fact, experimental results show that evolutionary techniques can be effectively adopted to tame randomness and exploit it in the ATPG process.…”

Section: Primary Outputsmentioning

confidence: 99%

“…Some of the advanced techniques recently introduced in GATrO and described in [6] can be usefully introduced in SAARA, too. As a future work we are also planning to eliminate the randomness in phase 1 by loading the same pattern from the end of the preceding phase 2.…”

Section: Conclusion and Future W O R Kmentioning

confidence: 99%

Saara

Corno

Prinetto

Rebaudenpgo

et al. 1997

Proceedings of the 1997 ACM Symposium on Applied Computing - SAC '97

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This paper deals with Automated Test Pattern Generation (ATPG) for large synchronous sequential circuits and describes a new approach based on Simulated Annealing. Simulation-based ATPG tools have several advantages with respect to deterministic and symbolic ones, especially because they can deal with large circuits. A prototypical system named SAARA is used to assess the effectiveness of the Simulated Annealing approach in terms of test quality and CPU time requirements. Results are reported, showing that SAARA is able to deal with large sequential circuits. A comparison with a state-of-the-art ATPG tool based on a Genetic Algorithm shows that SAARA generally improves the attained results in terms of fault coverage.

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“…GA has been considered as a possible approach to solve ATPG for sequential circuits in [1], [2] and [3]. The power of GA based ATPG mainly depends on the objective function which gives the fitness of a sequence.…”

Section: Introductionmentioning

confidence: 99%

A New Method of Test Generation for Sequential Circuits

Hou¹,

Zhao²,

Liao³

2006

2006 International Conference on Communications, Circuits and Systems

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The constant development of integrated circuits makes the automatic test pattern generation problem of sequential circuits a challenging area. Test generation procedures based on genetic algorithm (GA) have been showed to be effective in achieving high fault coverage. This paper presents a new approach to the test generation for synchronous sequential circuits. In this work, we address the problem of the automation test sequences generation based on particle swarm optimization (PSO) and fault simulation for sequential circuits. We emphasize three aspects: initialization, test sequence generation and test set compaction. Experimental results illustrate the effectiveness of the approach. PSO-based STPG is generally superior to GA-based STPG in terms of achieved fault coverage and required CPU time.

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Advanced techniques for GA-based sequential ATPGs

Abstract: Abstract

Cited by 37 publications

References 6 publications

Gate-level test generation for sequential circuits

Gate-level test generation for sequential circuits

Saara

A New Method of Test Generation for Sequential Circuits

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