Reduction of Test Power and Test Data Volume by Power Aware Compression Scheme

Sivanantham, S.; Manuel, Jincy P.; Sarathkumar, K.; Mallick, P. S.; Perinbam, J. Raja Paul

doi:10.1109/icacc.2012.36

Cited by 6 publications

(3 citation statements)

References 10 publications

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“…[7]) and X-filling technique [8], [9], [10], [11], [12], [13]. In the first approach, ATPG generates a fully specified test vectors incorporating several algorithm like test set compaction, reordering of test vector schemes so that the switching activity is reduced.…”

Section: Related Workmentioning

confidence: 99%

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Sivanantham

Sarathkumar

Manuel

et al. 2012

2012 International Symposium on Electronic System Design (ISED)

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In this paper, we present a new X-filling technique to reduce the shift and capture transitions occurred during scan based test application. The unspecified bits in the test cubes are filled with the logic value of 1's or 0's using the proposed don't care filling technique, namely CSP − f illing in such a way that the both average power and peak power in test applications are reduced. In our approach, the capture transition is made to be within the peak-power limit of the circuit under test while reducing the average power in shift-in phase of test applications. The experimental results obtained from ISCAS'89 benchmark circuits show that, the CSP − f illing technique provides a significant reduction in both shift and capture transitions in test mode.

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Section: Related Workmentioning

confidence: 99%

CSP-Filling: A New X-Filling Technique to Reduce Capture and Shift Power in Test Applications

Sivanantham

Sarathkumar

Manuel

et al. 2012

2012 International Symposium on Electronic System Design (ISED)

Self Cite

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“…The compression methods such as alternating FDR (ARL) coding [22], extended FDR (EFDR) coding [21,32], alternating variablelength (AVR) coding [24], equal-run-length coding (ERLC) [22], alternating frequency-directed equal-run-length coding (AFDER) [33], low-power selective pattern compression (LP-SPC), [34] and Shifted Alternating FDR coding [35] consider both runs of 0s as well as 1s to form the codewords. The ARL code [22] is also a variable-to-variable length code.…”

Section: Introductionmentioning

confidence: 99%

“…Several Huffman based compression techniques such as variable-input Huffman coding, variable-to-variable Huffman coding, optimal selective Huffman coding, complementary Huffman coding and run-length based Huffman coding (RLHC) available to improve the compression efficiency, area overhead and the test application time [37]. Many low-power compression techniques are available in the literature for the minimization of test power, test data volume and test time [8,[33][34][35]. In observation-oriented test pattern generation with the scan-chain disabling technique, the test pattern generation process is assisted by testability analysis to generate the observation-oriented test patterns.…”

Section: Introductionmentioning

confidence: 99%

Test Data Compression with Alternating Equal-Run-Length Coding

Sivanantham¹,

S²,

Ramki³

et al. 2018

IJET

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This paper presents a new X-filling algorithm for test power reduction and a novel encoding technique for test data compression in scan-based VLSI testing. The proposed encoding technique focuses on replacing redundant runs of the equal-run-length vector with a shorter codeword. The effectiveness of this compression method depends on a number of repeated runs occur in the fully specified test set. In order to maximize the repeated runs with equal run length, the unspecified bits in the test cubes are filled with the proposed technique called alternating equal-run-length (AERL) filling. The resultant test data are compressed using the proposed alternating equal-run-length coding to reduce the test data volume. Efficient decompression architecture is also presented to decode the original data with lesser area overhead and power. Experimental results obtained from larger ISCAS'89 benchmark circuits show the efficiency of the proposed work. The AERL achieves up to 82.05 % of compression ratio as well as up to 39.81% and 93.20 % of peak and average-power transitions in scan-in mode during IC testing.

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