Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs

Dastagiri, N. Bala; Kishore, K. Hari

doi:10.17485/ijst/2016/v9i43/104397

Cited by 6 publications

(3 citation statements)

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“…In this paper for multiplication a systematic Vedic multiplier is using Urdhava Tiryagbhyam. this Vedic multiplier occupies less area and performs faster multiplication among the all multipliers [13][14][15][16][17][18][19][20][21]. By using conventional multiplier, it reduces the typical calculation which is difficult to compute the formula Urdhava Tiryagbhyam is applicable for all types of multiplications.…”

Section: Vedic Multipliermentioning

confidence: 99%

Low power and high speed GDI based convolution using Vedic multiplier

Priyanka¹,

Kumar²,

Priya³

et al. 2018

IJET

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Convolution is having extensive area of application in Digital Signal Processing. Convolution supports to evaluate the output of a system with arbitrary input, with information of impulse response of the system. Linear systems features are totally stated by the systems impulse response, as ruled by the mathematics of convolution. Primary necessity of any application to work fast is that rise in the speed of their basic building block. Multiplier, adder is said to be the important building blocks in the process of convolution. As these blocks consumes plentiful time to obtain the response of the system. Several methods are designed to progress the speed of the Multiplier and adder, among all GDI (Gate Diffusion Input) is under emphasis because of faster working and low power consumption. In this paper GDI based convolution is implemented using Vedic multiplier and adder in T-SPICE Software which increases the speed and consumes less power compared to CMOS technology.

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Section: Vedic Multipliermentioning

confidence: 99%

Low power and high speed GDI based convolution using Vedic multiplier

Priyanka¹,

Kumar²,

Priya³

et al. 2018

IJET

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“…In this way, we get a total of 128 outputs from the comparison module each single output for 128 inputs. The distinct four inputs are combined to get a single output [14][15][16][17][18][19][20][21][22]. This procedure is tracked until we get our last 3 outputs.…”

Section: Architecturementioning

confidence: 99%

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Prasanna¹,

Sahiti²,

Raghuveera³

et al. 2018

IJET

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A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

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“…A Detailed scrutiny of various single edge triggered memory cells is studied in [13]. Low power very large scale integrated (VLSI) circuits have a great potential in the digital electronics.Dual-edge triggered (DET) flip-flops came into existence in the place of single edge triggered (SET) flip-flops [16][17][18][19]. As the DET flip-flops achieve the same data rate as of the SET flip-flops at half the clock frequency resulting in low power dissipation in the synchronous logic circuits.…”

mentioning

confidence: 99%

Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements

Priyadarshini,

Panda,

Sarvani

et al. 2019

IJRTE

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This research paper presents a low conditional discharge(C-element) Flip-Flops that are basic elements in all digital design. The existing circuits are power hunger due to the dynamic and static power dissipation increases. For reducing power consumption C element technique is used to reduce glitches at the data out. Results obtained through 130nm technology shows reduction in energy dissipation and delay. Average dynamic power dissipation of the proposed flip-flop is compare with two existing techniques. Average power of proposed flip-flop is reduced by 28.41% and 36.18% when compared with Latch-Mux flip-flop and Latch-Mux using Celement.

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Reduction of Kickback Noise in Latched Comparators for Cardiac IMDs

Cited by 6 publications

References 0 publications

Low power and high speed GDI based convolution using Vedic multiplier

Low power and high speed GDI based convolution using Vedic multiplier

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

Performance Analysis of Dual Edge Triggered Memory Cells using Multiple C-Elements

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