Reduction of IC Package Warpage through Finite Element Analysis and Direct Optimization

Moran, R L; Arriola, Emmanuel; Lim, N R E; Mercado, J P; Dimagiba, Richard; Gonzaga, Jeremias A.; Ubando, Aristotle T.

doi:10.1109/hnicem48295.2019.9072881

Cited by 5 publications

(2 citation statements)

References 9 publications

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“…The fundamental aim of this study is to investigate the distribution of Joule heating induced by variations in the area ratio between the metal line and via. To comprehensively explore this phenomenon, this study harnesses the powerful capabilities of the Ansys simulator (https://www.ansys.com), a widely respected and extensively used software tool in the realm of engineering simulations [16,17]. The selection of this advanced simulation platform ensures the accuracy and validity of the experimental outcomes, laying a robust foundation for the subsequent analysis.…”

Section: Methodsmentioning

confidence: 99%

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

Hong,

Kim,

Park

et al. 2023

Electronics

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This research was conducted in the context of the semiconductor market, with a demand for high-performance and highly integrated semiconductor systems that simultaneously enhance performance and reduce chip size. Scaling down the metal line and via in back-end-of-line (BEOL) structures is essential to efficiently deliver power to scaling down devices. This study utilized the finite element method (FEM) simulation technique to model the heat and current distribution for enhancing the efficiency of scaled-down structures. Due to current flow bottlenecks, an increase in the area ratio of the via to metal line (as the via becomes relatively smaller) leads to a temperature rise due to Joule heating. This trend follows a second-degree polynomial form, and the point where the temperature doubles compared to when the area ratio is one is situated at an area ratio of three. The temperature increase caused by Joule heating ultimately leads to destruction of the via, which directly affects the reliability of the BEOL structure. These experimental results can provide guidelines for designing with reliability considerations in mind, particularly in today’s semiconductor systems where significant scaling down is required in interconnect structures. They can also be widely applied to research aimed at developing interconnect structures that enhance reliability.

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Section: Methodsmentioning

confidence: 99%

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

Hong,

Kim,

Park

et al. 2023

Electronics

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“…Finite element analysis was performed in this study to assess the potential interfacial delamination in FOLWP driven by molded wafer warpage. FEA simulation is a widely used method to study the thermo-mechanical behavior of a semiconductor or microelectronic package [8,9]. It is a numerical technique through which a more detailed warpage behavior of the package can be predicted and visualized.…”

Section: Introductionmentioning

confidence: 99%

Interfacial Delamination Validation on Fan-Out Wafer-Level Package Using Finite Element Method

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Ubando

Gonzaga

2023

SSP

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Fan-out wafer-level package is a very promising packaging technology with good thermal and electrical performance. The fan-out wafer-level package exhibits beneficial features such as low profile, high I/O density, low cost, and efficient computing. The package experiences large temperature variations in the assembly phase which causes internal stresses. In particular, the mismatch between the coefficient of thermal expansion of the epoxy molding compound and the substrate due to the cool down phase of the cure process causes the internal stresses in the package. These internally induced stresses result to interfacial delamination. In this study, the interfacial delamination on a fan-out wafer-level package right after post mold cure of glass wafer was evaluated using the stress-based damage index through the finite element analysis in the ANSYS software package. The model was validated by comparing the simulation result of the glass wafer warpage to the existing experimental result from literature. From the warpage simulation of the glass wafer, the region on the package with high stress level was located and examined which may cause interfacial delamination. The maximum shear stress and principal stress at the epoxy molding compound and the Silicon chip interface was found to exceed the adhesion strength. This indicates that the interfacial delamination is inevitable. The information obtained from the stress analysis of molded wafer provides insight for the possible interfacial failure of fan-out wafer-level package in the individual package when subjected to thermomechanical loads.

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Warpage deformation analysis of AMB ceramic substrates in power modules

Hu,

Wang,

et al. 2024

2024 25th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and

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Reduction of IC Package Warpage through Finite Element Analysis and Direct Optimization

Cited by 5 publications

References 9 publications

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

Guidelines for Area Ratio between Metal Lines and Vias to Improve the Reliability of Interconnect Systems in High-Density Electronic Devices

Interfacial Delamination Validation on Fan-Out Wafer-Level Package Using Finite Element Method

Warpage deformation analysis of AMB ceramic substrates in power modules

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