Reducing TLB power requirements

Juan, Toni; Lang, T.; Navarro, Juan J.

doi:10.1145/263272.263332

Cited by 90 publications

(28 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…First, moving address translation into software creates a simpler and more flexible interface; as such, it supports much more innovation in the operating system than would a fixed design. Second, eliminating the TLB has the potential to reduce power consumption significantly [26]. Third, a reduction in hardware will leave room for more memory structures, perhaps helping to increase performance.…”

Section: Discussionmentioning

confidence: 99%

“…It shows that a software-oriented scheme can perform nearly as well as hardware schemes and it is more flexible. Eliminating dedicated special-purpose hardware from processor design can save chip area [25] and can reduce power consumption Ðe.g., the StrongARM TLB consumes 17 percent of the chip's power [26] and, so, eliminating the TLB would therefore reduce power consumption by a significant amount. Reducing die area and/or power potentially lowers the overall system cost.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Uniprocessor virtual memory without TLBs

Jacob

Mudge

2001

IEEE Trans. Comput.

View full text Add to dashboard Cite

AbstractÐWe present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, finegrained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardwaredefined mechanisms.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Uniprocessor virtual memory without TLBs

Jacob

Mudge

2001

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…In recent years, many new design methods are introduced to reduce the power consumption of TLB. The work described in [7] turns off some inactive entries of TLB according to history; [5] and [11] introduce micro-TLB, which divides TLB into two levels, and controls the number of entries accessed each time based on power considerations. But the hit rate of this method is much lower.…”

Section: Related Work and Experimental Methodologymentioning

confidence: 99%

An energy efficient TLB design methodology

Fan

Tang

Hai-lin

et al. 2005

Proceedings of the 2005 International Symposium on Low Power Electronics and Design - ISLPED '05

View full text Add to dashboard Cite

This paper researches Translation Look-aside Buffer (TLB) of embedded processor. Based on an analysis of design-related factors: power, area, critical path and performance of our research model-Godson-I, a low-power TLB design is proposed without sacrifice of performance and timing. Using this method, the following results are achieved: power of TLB-RAM reduces 92.7% and area of TLB-RAM reduces 50%. Compared with other methods, the hit rate of this design is much higher and the accessing conflict to RAM between ITLB and DTLB is much reduced. Although our work targets to Godson-I, the proposed methodology should be applicable to other designs.

show abstract

“…But for the data TLB, the performance degradation of the micro-TLB with respect to a fully associative TLB becomes significant. Other TLB studies address memory cell redesign, such as modified CAM cell [6], voltage reduction [7], and victim mechanism [8]. The work by Juan [6] proposes modifying the CAM cell by adding another transistor in the discharge path.…”

Section: Related Workmentioning

confidence: 99%

“…Other TLB studies address memory cell redesign, such as modified CAM cell [6], voltage reduction [7], and victim mechanism [8]. The work by Juan [6] proposes modifying the CAM cell by adding another transistor in the discharge path. With the modified cell, the control line can be used to precharge the match line without putting the bit lines to zero.…”

Section: Related Workmentioning

confidence: 99%

A banked-promotion TLB for high performance and low power

Lee

Jeong

et al.

Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001

View full text Add to dashboard Cite

This research is to design a simple but high performance TLB (translation lookaside buffer) system with low power consumption. Thus, we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub-fully associative TLBs. These two structures are integrated to form a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also energy dissipation can be reduced ,by around 50% comparing with the fully associative TLB.

show abstract

Reducing TLB power requirements

Cited by 90 publications

References 7 publications

Uniprocessor virtual memory without TLBs

Uniprocessor virtual memory without TLBs

An energy efficient TLB design methodology

A banked-promotion TLB for high performance and low power

Contact Info

Product

Resources

About