Uniprocessor virtual memory without TLBs

Abstract

AbstractÐWe present a feasibility study for performing virtual address translation without specialized translation hardware. Removing address translation hardware and instead managing address translation in software has the potential to make the processor design simpler, smaller, and more energy-efficient at little or no cost in performance. The purpose of this study is to describe the design and quantify its performance impact. Trace-driven simulations show that software-managed address translation is just as efficient as hardware-managed address translation. Moreover, mechanisms to support such features as shared memory, superpages, finegrained protection, and sparse address spaces can be defined completely in software, allowing for more flexibility than in hardwaredefined mechanisms.

Efficient virtual memory for big memory servers

“…For example, recent proposals increase the effective TLB size through co-operative caching of TLB entries [42] or a larger second-level TLB shared by multiple cores [7]. Prefetching was also proposed to hide the TLB miss latency [6,17,22]. SpecTLB [3] speculatively uses large-page translations while checking for overlapping base-page translations.…”

Generating physical addresses directly for saving instruction TLB energy

“…This work can be viewed as taking another step in the direction of removing the TLB altogether that was investigated in [17]. We are now less dependent on the actual iTLB structure in terms of its lookup latency.…”

“…At the same time, there are some drawbacks with VI-VT (even if we are to avoid cache aliasing with extra bits), since write-backs need to work with physical addresses -consequently, some VI-VT mechanisms keep both physical and virtual tags with each cache line to handle write-backs [15,17]. Our mechanisms, on the other hand, can take VI-PT and provide as good power savings as VI-VT (if not better) without incurring any performance degradation.…”

“…This also helps save realestate on-chip, in addition to power as mentioned in [17]. If cache misses become high (for some commercial workloads, even L2 misses can be quite important as reported in [1]), then the performance penalties can mitigate the benefits of this approach.…”

“…One could even try to extend the VI-VT lookup for the L2 cache as well. However, in this case, a hardware implementation can become cumbersome if the L2 is off-chip, and [17] suggests software-based TLB maintenance.…”