Reducing scan shifts using folding scan trees

Yotsuyanagi,; Kuchii,; Nishikawa,; Hashizume,; Kinoshita,

doi:10.1109/ats.2003.1250772

Cited by 16 publications

(7 citation statements)

References 11 publications

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“…It will make aliasing happen easily during compaction and be hard to design a compactor. To resolve such a problem, [15] extended the concept of compatibilities in [11][12][13][14], and proposed an extended compatibility scan tree construction. This method can reduce test application time and test power effectively.…”

Section: A Extended Compatibility Scan Treementioning

confidence: 99%

A response compactor for extended compatibility scan tree construction

You

Huang

Inoue

et al. 2009

2009 IEEE 8th International Conference on ASIC

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Section: A Extended Compatibility Scan Treementioning

confidence: 99%

A response compactor for extended compatibility scan tree construction

You

Huang

Inoue

et al. 2009

2009 IEEE 8th International Conference on ASIC

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“…Several tree-based scan architectures have been proposed [11], [12] earlier to reduce the test application time. Fig.…”

Section: Scan Tree Architecturementioning

confidence: 99%

“…In the ILS scan, several branches of the scan paths emanate from the scan-in pin of the circuit, which may cause overloading. An alternative approach, called scan tree has been proposed [10], [11], [12], [13] to reduce the test application time or test data volume. In such a scan architecture, the structure resembles a tree, where one cell drives other scan cells as in a tree.…”

Section: Introductionmentioning

confidence: 99%

An Efficient Scan Tree Design for Compact Test Pattern Set

Banerjee

Chowdhury

Bhattacharya

2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. However, these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage.

show abstract

“…Several tree-based scan architectures have been proposed [9,10] earlier to reduce the test application time. Fig.…”

Section: Scan Tree Architecturementioning

confidence: 99%

“…In the ILS scan, several branches of the scan paths emanate from the scan-in pin of the circuit, which may cause overloading. An alternative approach, called scan tree has been proposed [8,9,10,11] to reduce the test application time or test data volume. In such a scan architecture, the structure resembles a tree, where one cell drives other scan cells as in a tree.…”

Section: Introductionmentioning

confidence: 99%

An efficient scan tree design for compact test pattern set

Banerjee

Chowdhury

Bhattacharya

2006

19th International Conference on VLSI Design Held Jointly With 5th International Conference on Embedded Systems Design (VLSID'0

View full text Add to dashboard Cite

Various designs of scan paths based on tree-like structures have recently been suggested for reducing test application time or test data volume in today's high density VLSI circuits. Most of these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set, and therefore, are unsuitable for highly compact test sets generated by efficient ATPG tools. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture. Given a compact test set, compatibility relationships among the flip-flops are first explored, and a graph-based heuristic algorithm is employed to construct a scan tree with minimal incompatibility. Next, the same combinational ATPG tool is rerun to generate a new test set satisfying the logical constraints on the secondary inputs imposed by the structure of the scan tree. To cover the remaining hard-to-detect faults, if any, a few test vectors are chosen from the original test set for application in the serial mode. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing the total test application time significantly without any degradation of fault coverage.

show abstract

Reducing scan shifts using folding scan trees

Cited by 16 publications

References 11 publications

A response compactor for extended compatibility scan tree construction

A response compactor for extended compatibility scan tree construction

An Efficient Scan Tree Design for Compact Test Pattern Set

An efficient scan tree design for compact test pattern set

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