CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH374
DOI: 10.1109/ccece.2003.1226332
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Reducing power consumption in FPGA routing

Abstract: One of the mq'or drawbacks of field programmable gate arrays is their poor energy eficienq. This paper focuses on the routing phase of FPGA design and attempts to optimize dynamic power consumption in FPGA interconnect. Power optimization is performed with small side effects on circuit performance and area. Our enhancements to the VPR Timing Driven algorithm reduced the FPGA routing power by about IO% with negligible loss in circuitperformance.

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Cited by 5 publications
(2 citation statements)
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“…Then, using this model, some methods to reduce power consumption on FPGAs can be explored [5,7,8]. Finally, a tool that estimate the power consumption in FPGAs could be described.…”
Section: Power Consumption In Sram-based Fpgasmentioning
confidence: 99%
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“…Then, using this model, some methods to reduce power consumption on FPGAs can be explored [5,7,8]. Finally, a tool that estimate the power consumption in FPGAs could be described.…”
Section: Power Consumption In Sram-based Fpgasmentioning
confidence: 99%
“…Some authors propose to improve techniques to reduce power consumption using routing tools such as VPR [3,8]. In a previous work [4,6] a power consumption model was presented.…”
Section: Related Workmentioning
confidence: 99%