FPGA power consumption measurements and estimations under different implementation parameters

Meidanis, D.; Γεωργόπουλος, Κωνσταντίνος; Papaefstathiou, Ioannis

doi:10.1109/fpt.2011.6132694

Cited by 16 publications

(7 citation statements)

References 7 publications

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“…including the base consumption, the increase is 4%. This is well within the margin observed by [19] where different implementations of a design led to a difference of up to 10% in power consumption.…”

Section: Power Consumption Of Design Experimentssupporting

confidence: 84%

“…To derive the concept for the hands-on lab, it is investigated whether FPGAs can be used to experience different power consumption. In [19] it is shown, that the FPGA implementations of different security algorithms give measurable differences in power dissipation. The estimation tool of the FPGA supplier gives a pessimistic estimate compared to measurements [19] so it is no substitute for a lab exercise.…”

Section: A Hands-on Lab With Fpgasmentioning

confidence: 99%

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Addressing Low-Power Electronics in a Digital System and FPGA Design Course

Winzker

2014

Int. J. Eng. Ped.

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Low power dissipation is a current topic in digital design, and therefore, it should be covered in a state-of-the-art electrical engineering curriculum. This paper describes how low-power design can be addressed within a digital design course. Doing so would be beneficial for both topics because low-power design is not detached from the systems perspective, and the digital design course would be enriched by references to current challenges and applications. Thus, the presented course should serve as an example of how a course can be developed to also teach students about sustainable engineering.

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Section: Power Consumption Of Design Experimentssupporting

confidence: 84%

Section: A Hands-on Lab With Fpgasmentioning

confidence: 99%

Addressing Low-Power Electronics in a Digital System and FPGA Design Course

Winzker

2014

Int. J. Eng. Ped.

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“…In this study, we make use of the Xilinx ISE 14.4 [42] tool. Implementation settings, that can have a significant impact regarding the power consumption, have been set to a standard-level and default values have been retained to limit software optimizations [43]. All these remarks ensure the genericity of our approach.…”

Section: B Ip Characterization and Modellingmentioning

confidence: 99%

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

2016

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“…A very preliminary first step towards achieving this goal was taken at [12], which estimated the impact of different Xilinx's ISE optimization options on the power consumption of different security algorithms. However, that study considered just 4 different options (only one of them was related to the synthesis process), and focused on just one primary goal (power consumption).…”

Section: Introductionmentioning

confidence: 99%

Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study

Tuzov

Andrés

Ruíz

2018

Journal of Parallel and Distributed Computing

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The steady growth in complexity of FPGAs have led designers to rely more and more on manufacturers' and third parties' design tools to meet their implementation goals. However, as modern synthesis tools provide a myriad of different optimization flags, whose contribution towards each implementation goal is not clearly accounted for, designers just make use of a handful of those flags. This paper addresses the challenging problem of determining the best configuration of available synthesis flags to optimize the designers implementation goals. First, fractional factorial design is used to reduce the whole design space. Resulting configurations are implemented to estimate the actual impact, and statistical significance, of each considered synthesis flag. After that, multiple regression analysis techniques predict the expected outcome for each possible combination of these flags. Finally, multiple-criteria decision making techniques enable the selection of the best set of synthesis flags according to explicitly defined implementation goals.

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FPGA power consumption measurements and estimations under different implementation parameters

Cited by 16 publications

References 7 publications

Addressing Low-Power Electronics in a Digital System and FPGA Design Course

Addressing Low-Power Electronics in a Digital System and FPGA Design Course

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

Tuning synthesis flags to optimize implementation goals: Performance and robustness of the LEON3 processor as a case study

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