Reducing misprediction penalty in the Branch Target Buffer

Abstract

Ideal speedup in pipelined processors is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards, the latter, however, can be the most detrimental to pipeline performance. Branch Target Buffer (BTB) can reduce performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in BTB and the prediction is correct; otherwise, the penalty will be at least two cycles. This paper proposes a novel algorithm based on changing the BTB structure to eliminate the branch misprediction penalty. It also highlights a problem in the previous BTB algorithms (nested branches problem) and proposes a solution to it.

Implementation of branch delay in Superscalar processors by reducing branch penalties

“…They are divided into two categories: (1) those which save the target instruction(s) without the target address, (2) those which save the target instruction(s) in addition to the target address .In the first case, the target address should be eventually calculated before fetching can start, which introduces an unnecessary delay [7]. These two categories, however, assumed that the cached instruction could be directly fed into the pipeline, skipping the fetch stage.…”

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

“…It is necessary to consider performance improvement and power consumption during a processor design. Although most processors use a delayed branch for normal pipeline operations, pipeline operation delay caused by a delayed branch has become a serious obstacle for improving performance [1][2][3][4].Caches have become the most basic and the most important elements determining the performance of high performance microprocessors with unsatisfyingly limited memory bandwidth provided by the systems. In addition, most of the dynamic power of a processor is dissipated on the clock and data-path related circuits.…”

“…It is necessary to consider performance improvement and power consumption during a processor design. Although most processors use a delayed branch for normal pipeline operations, pipeline operation delay caused by a delayed branch has become a serious obstacle for improving performance [1][2][3][4].…”