Reducing memory access latency with asymmetric DRAM bank organizations

Abstract

DRAM has been a de facto standard for main memory, and advances in process technology have led to a rapid increase in its capacity and bandwidth. In contrast, its random access latency has remained relatively stagnant, as it is still around 100 CPU clock cycles. Modern computer systems rely on caches or other latency tolerance techniques to lower the average access latency. However, not all applications have ample parallelism or locality that would help hide or reduce the latency. Moreover, applications' demands for memory space continue to grow, while the capacity gap between last-level caches and main memory is unlikely to shrink. Consequently, reducing the main-memory latency is important for application performance. Unfortunately, previous proposals have not adequately addressed this problem, as they have focused only on improving the bandwidth and capacity or reduced the latency at the cost of significant area overhead. We propose asymmetric DRAM bank organizations to reduce the average main-memory access latency. We first analyze the access and cycle times of a modern DRAM device to identify key delay components for latency reduction. Then we reorganize a subset of DRAM banks to reduce their access and cycle times by half with low area overhead. By synergistically combining these reorganized DRAM banks with support for non-uniform bank accesses, we introduce a novel DRAM bank organization with center high-aspect-ratio mats called CHARM. Experiments on a simulated chip-multiprocessor system show that CHARM improves both the instructions per cycle and system-wide energy-delay product up to 21% and 32%, respectively, with only a 3% increase in die area.

Adaptive-latency DRAM: Optimizing DRAM timing for the common-case

“…To establish a more quantitative relationship between charge and latency, Figure 3 presents the voltage of a cell and its bitline as they cycle through the precharged state, charge-sharing state, sense-amplification state, restored state, and back to the precharged state (Section 2). 1 This curve is typical in DRAM operation, as also shown in prior works [14,27,36,66]. The timeline starts with an ACTIVATE at 0 ns and ends with the completion of PRECHARGE at 48.75 ns.…”

“…Several works investigated the possibility of reducing DRAM latency by either exploiting DRAM latency variation [7,65] or changing the DRAM architecture [34,36,45,61,62,66]. We discuss these below.…”

“…To store data in a cell, charge is injected, whereas to retrieve data from a cell, charge is extracted. Such movement of charge is not only the centerpiece of DRAM operation, but also the bottleneck of DRAM latency [36,66]. This is due to two fundamental reasons.…”

“…This is due to two fundamental reasons. First, when injecting charge into a cell, a wire called the bitlinethrough which the charge is delivered -impedes the flow of charge [36,66]. Owing to the large resistance and the large capacitance of the bitline, the cell experiences a large RC-delay, which increases the time it takes for the cell to become fully charged.…”

“…Owing to the large resistance and the large capacitance of the bitline, the cell experiences a large RC-delay, which increases the time it takes for the cell to become fully charged. Second, when extracting charge from a cell, the cell is incapable of mobilizing a strong flow of charge out of itself and into the bitline [36,66]. Limited by the finite amount of charge stored in its small capacitor, the cell has an inherently weak charge-drive, which is further weakened as the cell loses more of its charge to the bitline.…”