Reduced geometry CMOS technology

Abstract

AJ3STRAIXTn this presentation, the authors review bulk silicon CMOS evolution and discuss the suitability of scaling CMOS to one micron features. Characterization data from one micron twin-tub processes fabricated on both n and p-type starting material will be reviewed. These data include latch-up sensitivity of the technology in which the dramatic improvement achievable with retrograde implantation will be highlighted. The outstanding performance achievable with reduced geometry will be emphasized with data obtained from a dual modulus prescaler which has operated at clock rates in excess of 1 Ghz at 5 volts. INTRODUIXIONThe recent emergence of bulk silicon CMOS technology in high volume memory and microprocessor components has made it a leading candidate to become the mainstream VLSI technology of the 80's. CMOS is an attractive technology choice at reduced geometries because of the low power and high performance which can be achieved. In this presentation, the authors will discuss the evolution of CMOS and it s future opportunity as features are scaled to one micron. Twin-tub approaches utilizing both p and n type starting material (n-well and pwell) will be reviewed in detail. Characterization data presented will emphasize the importance circuit latch-up plays in the development of a one micron CMOS technology. Performance data obtained from digital and analog circuits fabricated with a 1.2 micron retrograde p-well CMOS technology will be highlighted. CMOS EVOLUTIONThe initial work in bulk silicon CMOS, prompted by military requirements, was directed at achieving low stand-by power and radiation immunity. The metal gate p-well process which emerged in the late 60's employed both well guardbands and transistor channel stops to enhance device isolation and minimize latch-up. At that time, a p-well approach was a logical choice. Diffusion of the pwell into a lightly doped n type substrate increased the p-well surface doping and insured that NMOS transistors would be enhancement mode and have a natural threshold nearly symmetrical to that of the PMOS device. Furthermore, the gain constant difference between NMOS and PMOS was minimized by fabricating the PMOS in the lightly-doped substrate where the mobility is higher, permitting a more symmetrical layout.The p-well approach became classic and innovation was concentrated on other process aspects. Self-aligned silicon gates were introduced along with threshold adjustment by boron ion implantation in 1972. Four years later, a fully plasma etched, ion implanted CMOS process was reported [ll. The remarkable aspect of this process was the replacement of guard bands with buried oxide isolation. In addition, the polysilicon gate was singly-doped(N+) to enhance conductivity and eliminate the need for metal bridging between N+ and P+ polysilicon evident in earlier silicon gate CMOS processes. These innovations set new standards of high density and performance for M O S and represented the mainstream CMOS technology of the 70's. A major step in CMOS evolution occurred with ...

Low‐Energy Contaminant in B++ Implantation and Its Elimination

“…High-energy ion implantation is a particularly attractive technique for producing isolation p-and n-wells in CMOS technology. In the GE A/VLSI technology (1,2), high-energy boron implants are used to form retrograde p-wells to enhance device performance in a radiation environment and to reduce latchup of devices in circuits. Such applications require boron ion energies in excess of 200 keV.…”