Reduced area discrete-time down-sampling filter embedded with windowed integration samplers

Abstract

A technique to implement a discrete-time (DT) sinc 3 2 filter for windowed integration samplers is proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33% of the die area compared to the currently existing topology. Circuit level simulations in 45 nm CMOS technlogy shows good agreement with the predicted behaviour obtained from the analaysis.Introduction: Developing a flexible receiver which can be reconfigured to multiple standards is the key to solving the problem of embedding numerous and ever-changing functionalities in mobile handsets. Difficulty in efficiently reconfiguring analogue blocks of a receiver chain to multiple standards calls for moving the ADC as close to the antenna as possible so that most of the signal processing is done in the digital domain. To this end, [1] discusses an architecture wherein the signal at RF, after being down-converted to DC with a broadband LNA and mixer, is digitised with minimum analogue processing. Apart from requiring anti-blocking at other frequencies, sampling at f s will require a high attenuation at f s , 2f s . . . nf s to avoid aliasing by sampling images. Different standards are sampled at different frequencies and a programmable anti-aliasing filtering is needed here. Windowed integration samplers have an inherent sinc filtering which creates nulls at f s and its multiples. Since the attenuation provided by such samplers for a given bandwidth is proportional to the sampling frequency, a high-rate sampling followed by a down-sampling filter and high order anti-aliasing filter (sinc 2 and sinc 3 ) [1, 2] to attenuate unwanted signals that fold back into the desired bandwidth, is required. Fig. 1 shows the magnitude responses of sinc, sinc 2 and sinc 3 finiteimpulse-response (FIR) filters. The idea for implementing a sinc 2 filter proposed in [1, 2] and a sinc 3 filter in [2] involves the use of several switches and sampling capacitors that consumes a considerable amount of the die area which increases the production cost. To this end, this Letter addresses the issue of reducing the die area of sinc 3 2 filters for windowed integrations samplers by minimising the time for which the capacitors are idle. Also, a capacitor added at the output of the transconductor gives a discrete-time infinite-impulseresponse (DT-IIR) [1] effect apart from reducing overshoots in voltage [2]. Comparison with the previously proposed technique presented in the following Section reveals that the proposed scheme saves 33% of the sampling capacitors area.