Redistribution Layers (RDLs) for 2.5D/3D IC Integration

Lau, John H.; Tzeng, Pei-Jer; Lee, C.; Zhan, Cheng; Li, M.; Cline, Julia R. K.; Saito, Keisuke; Hsin, Yu-Chen; Chang, Phei‐Lang; Chang, Yu Han; Chen, J.; Chen, S.; Wu, Chia‐Lin; Chang, Hwan‐You; Chien, Chun-Hsien; Lin, Cheng‐Hsiung; Ku, T. K.; Lo, R.; Kao, Ming-Jer

doi:10.4071/isom-2013-wa12

Cited by 16 publications

(4 citation statements)

References 6 publications

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“…RDLs are usually fabricated by combining photolithographic processes with sputtering and plating. [ 294 ] Employing FOWLP for MEMS sensor packaging has some unique challenges, particularly if delicate devices such as capacitive micromachined ultrasound transducers are involved. The RDL must be removed above the membrane to ensure proper functionality of the sensor.…”

Section: Applicationsmentioning

confidence: 99%

Printed Electronics Technologies for Additive Manufacturing of Hybrid Electronic Sensor Systems

Zikulnig

Chang

Bito³

et al. 2023

Advanced Sensor Research

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Requirements for the miniaturization of electronics are constantly increasing as more and more functions are aimed to be integrated into a single device. At the same time, there are strong demands for low-cost manufacturing, environmental compatibility, rapid prototyping, and small-scale productions due to fierce competition, policies, rapid technical progress, and short innovation times. Altogether, those challenges cannot be sufficiently addressed by simply using either printed or silicon electronics. Instead, the synergies from combining those two technologies into so-called hybrid electronics create novel opportunities for advanced capabilities and new areas of applications. In the first part of this review, printing and patterning technologies are presented with potential compatibility with conventional electronics manufacturing techniques. They can be utilized for the fabrication of highly complex structures. Nonetheless, up-scalability, integration, and adaptation for industrial fabrication remain challenging due to technically limiting factors. Consequently, a special focus is placed on the up-scalability, availability of commercial printing, and manufacturing machines, as well as processing challenges for high-volume industrial applications. The second part of this review further provides an overview of exciting and innovative application possibilities of printed electronics, emphasizing sensor applications, as well as additively manufactured integrated circuits.

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Section: Applicationsmentioning

confidence: 99%

Printed Electronics Technologies for Additive Manufacturing of Hybrid Electronic Sensor Systems

Zikulnig

Chang

Bito³

et al. 2023

Advanced Sensor Research

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“…Redistribution layers [104][105][106][107] are the most integral part of wafer-level packaging (WLP). The RDL consists of two layers, the dielectric layer and the Cu conducting layer.…”

Section: Redistribution Layers Fabricationsmentioning

confidence: 99%

“…29. This is called the dual Cu-damascene method [104,105]. Finally, repeat all the processes to get the other RDLs.…”

Section: Journal Of Electronic Packagingmentioning

confidence: 99%

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Lau

2019

Journal of Electronic Packaging

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The recent advances and trends in fan-out wafer/panel-level packaging (FOW/PLP) are presented in this study. Emphasis is placed on: (A) the package formations such as (a) chip first and die face-up, (b) chip first and die face-down, and (c) chip last or redistribution layer (RDL)-first; (B) the RDL fabrications such as (a) organic RDLs, (b) inorganic RDLs, (c) hybrid RDLs, and (d) laser direct imaging (LDI)/printed circuit board (PCB) Cu platting and etching RDLs; (C) warpage; (D) thermal performance; (E) the temporary wafer versus panel carriers; and (F) the reliability of packages on PCBs subjected to thermal cycling condition. Some opportunities for FOW/PLP will be presented.

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“…The 2.5D/3D Integrated packaging is seen as an effective technology to satisfy the requirements, e.g., higher input/output (I/O) density, excellent signal integrity, and outstanding heat dissipation, for nano/micro electronic systems [8][9][10][11]. The bump, through silicon via (TSV) and redistribution layer (RDL), comprises the essential components for 2.5D/3D integrated devices [12][13][14]. Among them, the functions of electric conduction, thermal conduction, and mechanical connection between TSV and RDL were realized by bumps.…”

Section: Introductionmentioning

confidence: 99%

Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging

et al. 2022

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With the rapid development of nano/micro technology for commercial electronics, the typical interconnection method could not satisfy the high power-density packaging requirement. The 2.5D/3D integrated packaging was seen as a promising technology for nano/micro systems. The gold (Au) bump was the frequently used bonding method for these systems because of its excellent thermal, electric, and mechanical performance. However, relatively little work has been performed to analyze its height uniformity. In this study, the simulation and experimental methods were used to analyze the Au bump height uniformity. Firstly, the electroplating process of Au bump under different flow field parameters was simulated by COMSOL software. The simulated results indicated that the Au+ concentration polarization was the significant reason that caused the non-uniform distribution of Au bump along the wafer radius. Meanwhile, the flow field parameters, such as inlet diameter, inlet flow, titanium (Ti), wire mesh height, and Ti wire mesh density, were optimized, and their values were 20 mm, 20 L/min, 12 mm, and 50%, respectively. Subsequently, the Au bump height uniformity under different current densities was analyzed through an experimental method based on these flow field parameters. The experimental results showed that the increases of current density would decrease the Au bump height uniformity. When the current density was 0.2 A/dm2, the average height, range, and deviance values of Au bump were 9.04 μm, 1.33 μm, and 0.43 μm, respectively, which could reach the requirement of high density and precision for 2.5D/3D integrated packaging.

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Redistribution Layers (RDLs) for 2.5D/3D IC Integration

Cited by 16 publications

References 6 publications

Printed Electronics Technologies for Additive Manufacturing of Hybrid Electronic Sensor Systems

Printed Electronics Technologies for Additive Manufacturing of Hybrid Electronic Sensor Systems

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

Height Uniformity Simulation and Experimental Study of Electroplating Gold Bump for 2.5D/3D Integrated Packaging

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