REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

Satrawala, A.N.; Varadarajan, Keshavan; Ma, Lianjie; Nandy, S. K.; Narayan, Ranjani

doi:10.1109/fpl.2007.4380716

Cited by 9 publications

(4 citation statements)

References 2 publications

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“…Many recent architectures developed in academia include Morpheus [13], Montium/Chameleon system from University of Twente [14], Adres [15] from IMEC in Belgium, Imagine [16] from Univ. of Stanford and REDEFINE from Morphing Machines [17]. A comprehensive survey of academic CGRAs has been done recently by Max Baron [18] for largely commercial CGRAs.…”

Section: Reviewmentioning

confidence: 99%

reMORPH: A Runtime Reconfigurable Architecture

Paul

Dash

Moghaddam

2012

2012 15th Euromicro Conference on Digital System Design

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Programmable hardware built on a regular architecture can partially alleviate the problem of increased defect densities associated with transistor scaling by dynamically wiring around the defects [1]. The fine granularity of FPGAs is however unsuitable for effectively exploiting runtime reconfiguration because of the high overheads involved. A coarse grain reconfigurable array with malleable communication links -reMORPH -is proposed in this paper. The compute tile uses DSP48E and BRAM embedded blocks in a Xilinx FPGA and has a very low footprint of about 200 slice LUTs. The semi-systolic near neighbour communication interconnect can be dynamically reconfigured for each "epoch" of computation. The "epoch" or phases of the application are obtained via profiling or static data flow analysis. Some of the links between the compute tiles are changed during the reconfiguration phase which drastically reduces the context switch overhead enabling high performance/area applications to be built on this fabric.

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Section: Reviewmentioning

confidence: 99%

reMORPH: A Runtime Reconfigurable Architecture

Paul

Dash

Moghaddam

2012

2012 15th Euromicro Conference on Digital System Design

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“…FPGAs, MP-SOCs and hardware accelerators proposed as solutions in the recent past fail to provide run-time interoperability between applications and their derivatives because of their inability to simultaneously meet the constraints of high performance, low-power and scalability. An SoC fabric that is defined in terms of run-time reconfigurable hardware modules [12] bears the potential to meet some of the above requirements.…”

Section: Introductionmentioning

confidence: 99%

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders

Adrsha

Mythri

Nandy

et al. 2008

2008 International Conference on Application-Specific Systems, Architectures and Processors

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Run-time interoperability between different applications based on H.264/AVC is an emerging need in networked infotainment, where media delivery must match the desired resolution and quality of the end terminals. In this paper, we describe the architecture and design of a polymorphic ASIC to support this. The H.264 decoding flow is partitioned into modules, such that the polymorphic ASIC meets the design goals of low-power, low-area, high flexibility, high throughput and fast interoperability between different profiles and levels of H.264. We demonstrate the idea with a multi-mode decoder that can decode baseline, main and high profile H.264 streams and can interoperate at run-time across these profiles. The decoder is capable of processing frame sizes of up to 1024×768 at 30 fps. The design synthesized with UMC 0.13µm technology, occupies 250k gates and runs at 100MHz.

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“…Examples of this network are mesh, honeycomb, etc. Honeycomb has a lower degree per node than a 2-D Mesh [12]. This reduces the complexity and area of the network router.…”

Section: Introductionmentioning

confidence: 99%

“…REDEFINE [3,12] hardware resources, comprise Compute Elements (CEs) with local storage and routers that communicate over network on chip (NoC) as in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

Singh¹,

Alle²,

Vardarajan³

et al. 2010

IJCA

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REDEFINE [3] is a polymorphic ASIC, in which arbitrary computational structures on hardware are defined at runtime. The REDEFINE execution fabric comprises Compute Elements (CEs) interconnected by a Honeycomb network, which also serves as the distributed Network-on-chip. Each computational structure is dynamically assigned to a subset of the CEs on the execution fabric by the REDEFINE support logic. A HLL specification of the application is compiled into Hyper Operations (HyperOps) by the REDEFINE compiler [3], where each HyperOp is a set of interacting operations. The compiler also determines partitions of the HyperOps (pHyperOps) that can be assigned to CEs to suitably meet the structural constraints of the execution fabric. In this paper we propose an algorithm to map HyperOps onto Computational Structures. A pHyperOp communication graph (PCG) captures the communication between the various pHyperOps. Through a sequence of transformations, the PCG is transformed into a Cayley tree. The Cayley tree is then overlayed on the Cayley graph to form a computational structure. The proposed mapping algorithm offers a solution that incurs a penalty 18% on average over that of the optimal.

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REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures

Cited by 9 publications

References 2 publications

reMORPH: A Runtime Reconfigurable Architecture

reMORPH: A Runtime Reconfigurable Architecture

Architecture of a polymorphic ASIC for interoperability across multi-mode H.264 decoders

A Generic Graph-Oriented Mapping Strategy for a Honeycomb Topology

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