Recursive array layouts and fast parallel matrix multiplication

Chatterjee, Siddhartha; Lebeck, Alvin R.; Patnala, Praveen K.; Thottethodi, Mithuna

doi:10.1145/305619.305645

Cited by 87 publications

(105 citation statements)

References 30 publications

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“…Their layout is very similar to one of the 4D layouts mentioned in [1,2]. Their work, similar to ours, also considers non-tiled or non-recursive algorithms but does not discuss padding.…”

Section: Previous Workmentioning

confidence: 69%

“…Notably, Wise et al [8], Chatterjee et al [1,2], and Gustavson [4] pioneered these layouts, focusing on optimizing for temporal locality. Their implementations are either tiled or recursively formulated.…”

Section: Previous Workmentioning

confidence: 99%

“…Their implementations are either tiled or recursively formulated. In [4] Gustavson adopts a similar approach to Chatterjee [1,2]; however, Gustavson's work is focused on deriving optimal layouts for particular problems rather than a generic solution.…”

Section: Previous Workmentioning

confidence: 99%

“…Many authors [1][2][3] have identified that such a complete decomposition may lead to increased conflict misses between different blocks, and have proposed different variants to fully recursive layouts. Chatterjee et al [1] propose a family of non-linear alternative layouts, called 4D layouts, which intermix recursive and linear layouts.…”

Section: Previous Workmentioning

confidence: 99%

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Minimizing Associativity Conflicts in Morton Layout

Thiyagalingam

Beckmann

2006

Lecture Notes in Computer Science

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Abstract. Hierarchically-blocked non-linear storage layouts, such as the Morton ordering, have been shown to be a potentially attractive compromise between row-major and column-major for two-dimensional arrays. When combined with appropriate optimizations, Morton layout offers some spatial locality whether traversed row-or column-wise. However, for linear algebra routines with larger problem sizes, the layout shows diminishing returns. It is our hypothesis that associativity conflicts between Morton blocks cause this behavior and we show that carefully arranging the Morton blocks can minimize this effect. We explore one such arrangement and report our preliminary results.

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“…Their layout is very similar to one of the 4D layouts mentioned in [1,2]. Their work, similar to ours, also considers non-tiled or non-recursive algorithms but does not discuss padding.…”

Section: Previous Workmentioning

confidence: 69%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

Minimizing Associativity Conflicts in Morton Layout

Thiyagalingam

Beckmann

2006

Lecture Notes in Computer Science

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“…See Chatterjee et al [11,12] for further details and implementation issues for this layout. Like the cache-oblivious algorithm, this algorithm also uses recursion to divide the problem into smaller subproblems until it reaches an architecture-specific tile size, where it performs the exchanges.…”

Section: Algorithm 6: Non-linear Array Layoutmentioning

confidence: 99%

Cache-efficient matrix transposition

Chatterjee

Sen

Proceedings Sixth International Symposium on High-Performance Computer Architecture. HPCA-6 (Cat. No.PR00550)

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We investigate the memory system performance of several algorithms for transposing an N N matrix in-place, where N is large. Specifically, we investigate the relative contributions of the data cache, the translation lookaside buffer, register tiling, and the array layout function to the overall running time of the algorithms. We use various memory models to capture and analyze the effect of various facets of cache memory architecture that guide the choice of a particular algorithm, and attempt to experimentally validate the predictions of the model. Our major conclusions are as follows: limited associativity in the mapping from main memory addresses to cache sets can significantly degrade running time; the limited number of TLB entries can easily lead to thrashing; the fanciest optimal algorithms are not competitive on real machines even at fairly large problem sizes unless cache miss penalties are quite high; low-level performance tuning "hacks", such as register tiling and array alignment, can significantly distort the effects of improved algorithms; and hierarchical nonlinear layouts are inherently superior to the standard This work is supported in part by DARPA Grant DABT63-98-1-0001, NSF Grants CDA-97-2637 and CDA-95-12356, The University of North Carolina at Chapel Hill, Duke University, and an equipment donation through Intel Corporation's Technology for Education 2000 Program. The views and conclusions contained herein are those of the authors and should not be interpreted as representing the official policies or endorsements, either expressed or implied, of DARPA or the U.S. Government. canonical layouts (such as row-or column-major) for this problem.

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Cache‐oblivious matrix algorithms in the age of multicores and many cores

Heinecke

Trinitis

2012

Concurrency and Computation

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SummaryThis article highlights the issue of upcoming wider single‐instruction, multiple‐data units as well as steadily increasing core counts on contemporary and future processor architectures. We present the recent port to and latest results of cache‐oblivious algorithms and implementations of our TifaMMy code on four architectures: SGI's UltraViolet distributed shared‐memory machine, Intel's latest x86 architecture code‐named Sandy Bridge, AMD's new Bulldozer architecture, and Intel's future Many Integrated Core architecture. TifaMMy's matrix multiplication and LU decomposition routines have been adapted and tuned with regard to these architectures. Results are discussed and compared with vendors’ architecture‐specific and optimized libraries, Math Kernel Library and AMD Core Math Library, for both a standard C++ version with vectorization compiler switches and TifaMMy's highly optimized vector intrinsics version. We provide insights into architectural properties and comment on the feasibility of heterogeneous cores and accelerators, namely graphics processing units. Besides bare‐metal performance, the test platforms’ ease of use is analyzed in detail, and the portability of our approach to new and upcoming silicon is discussed with regard to required effort on code change abstraction levels.As a result, we demonstrate that because of its generic structure in terms of memory organization, TifaMMy executes with equally efficient performance on all four architectures as it automatically adapts itself to architectural parameters without losing performance against the Math Kernel Library and AMD Core Math Library, underlining its generic and cache‐oblivious properties, as the porting effort was relatively low compared with that in other implementations.Copyright © 2012 John Wiley & Sons, Ltd.

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Recursive array layouts and fast parallel matrix multiplication

Cited by 87 publications

References 30 publications

Minimizing Associativity Conflicts in Morton Layout

Minimizing Associativity Conflicts in Morton Layout

Cache-efficient matrix transposition

Cache‐oblivious matrix algorithms in the age of multicores and many cores

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