Cache‐oblivious matrix algorithms in the age of multicores and many cores

Abstract

SummaryThis article highlights the issue of upcoming wider single‐instruction, multiple‐data units as well as steadily increasing core counts on contemporary and future processor architectures. We present the recent port to and latest results of cache‐oblivious algorithms and implementations of our TifaMMy code on four architectures: SGI's UltraViolet distributed shared‐memory machine, Intel's latest x86 architecture code‐named Sandy Bridge, AMD's new Bulldozer architecture, and Intel's future Many Integrated Core architecture. TifaMMy's matrix multiplication and LU decomposition routines have been adapted and tuned with regard to these architectures. Results are discussed and compared with vendors’ architecture‐specific and optimized libraries, Math Kernel Library and AMD Core Math Library, for both a standard C++ version with vectorization compiler switches and TifaMMy's highly optimized vector intrinsics version. We provide insights into architectural properties and comment on the feasibility of heterogeneous cores and accelerators, namely graphics processing units. Besides bare‐metal performance, the test platforms’ ease of use is analyzed in detail, and the portability of our approach to new and upcoming silicon is discussed with regard to required effort on code change abstraction levels.As a result, we demonstrate that because of its generic structure in terms of memory organization, TifaMMy executes with equally efficient performance on all four architectures as it automatically adapts itself to architectural parameters without losing performance against the Math Kernel Library and AMD Core Math Library, underlining its generic and cache‐oblivious properties, as the porting effort was relatively low compared with that in other implementations.Copyright © 2012 John Wiley & Sons, Ltd.

A Novel Hilbert Curve for Cache-Locality Preserving Loops

“…Our algorithm FUR-Hilbert, as discussed in Section 5, is implemented in C++ and compiled with gcc version 4.9.2. We compare our algorithm to the algorithm "TifaMMy" for matrix multiplication based on the Peano Curve introduced by Bader et al [11], [12] (source code has been obtained by the authors compiled with icc version 16.0.3). Furthermore we compare our algorithm to the specifically for Intel processors hardware-and hand-optimized Intel MKL library (https://software.intel.com/en-us/intel-mkl) version 11.3 (operation: dgemm).…”

“…The cache hit rate for "perf" is calculated as: 1 − cache-misses:u cache-references:u . We use the maximum number of threads (12) for the variation in problem size and matrices of size 10 000 are processed for the variation of threads. Figure 10 illustrates the cache hit rate for each cache level respectively and the cache hit rate for the entire cache hierachy.…”

“…In [12], [19] Bader et al present variants of their algorithms for matrix operations. As in [11], [13], the general algorithmic scheme is recursive partitioning according to the Peano curve.…”

Recent developments in high‐performance computing and simulation: distributed systems, architectures, algorithms, and applications

“…‘Cache‐oblivious Matrix Algorithms in the Age of Multi‐ and Many‐Cores’ by Alexander Heinecke and Carsten Trinitis highlights the issue of increasing vector unit width that goes along with increasing core counts on x86 processor architectures. To demonstrate this, a cache‐oblivious numerical code has been ported to and optimized on four contemporary x86 architectures representing vector unit widths from 128 to 512 bits.…”