Reconfigurable tester hardware extends JTAG/boundary scan applications while simplifying ate setup

Ehrenberg, H.

doi:10.1109/autest.2007.4374289

Cited by 3 publications

(2 citation statements)

References 5 publications

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“…Boundary scan takes less time for testing depending upon the complexity of the circuit. Furthermore, some circuit nodes connecting two or more BGA (Ball Grid Array) pins may never have surface to test so it makes boundary scan the only way of quality testing [13]. [14].…”

Section: Introductionmentioning

confidence: 99%

A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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Over the past years complexity of PCB board and the surface mount technology has increased by leaps and bounds. This limits the use of traditional in-circuit test techniques for testing of such boards. This paper addresses the various issues of board level interconnect testing using Boundary Scan architecture. This work implements BIST using Boundary Scan technique. A new Algorithm is developed to diagnose PCB level faults. The dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults are taken up in this paper. The proposed algorithm is also compared with the existing algorithms viz modified counting, walking one's algorithm and others. Our results are found to be better than the existing algorithms.

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Section: Introductionmentioning

confidence: 99%

A novel method for diagnosis of board level interconnect faults using boundary scan

Kumar

Sharma

et al. 2010

2010 International Conference on Computer and Communication Technology (ICCCT)

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“…Boundary scan takes less time for testing depending upon the complexity of the circuit. Furthermore, some circuit nodes connecting two or more ball grid array pins may never have surface to test, so it makes boundary scan the only way of quality testing (Ehrenberg, 2007). In current trends, industries are using IEEE 1149.1 boundary scan standard to test the heavily loaded PCB as this method is cost effective and have no need of physical probing (Parker, 1992;Lofstrom, 1996;Hur and Lim, 1994;Lee et al, 1998).…”

Section: Introductionmentioning

confidence: 99%

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Sharma¹,

Sharma

Kaushik

et al. 2011

Circuit World

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Purpose -This paper aims to address the various issues of board-level (off-chip) interconnects testing. A new algorithm based on the boundary scan architecture is developed to test off-chip interconnect faults. The proposed algorithm can easily diagnose which two interconnects are shorted. Design/methodology/approach -The problems in board-level interconnects testing are not simple. A new algorithm is developed to rectify some of the problems in existing algorithms. The proposed algorithm to test board-level interconnect faults is implemented using Verilog on Modelsim software. The output response of each shorting between different wires of different nodes is different, which is the basis of fault detection by the proposed algorithm. The test vectors are generated by the test pattern generator and these test vectors are different for different nodes. This work implements built in self test using boundary scan technique. Findings -The dominant-1 (wired-OR, denoted as WOR), dominant-0 (wired-AND, denoted as WAND) and stuck-at faults are tested using the proposed algorithm. The proposed algorithm is also compared with the several algorithms in the literature, i.e. modified counting, walking one's algorithm and others. This paper's results are found to be better than the existing algorithms.Research limitations/implications -The limitation of the proposed algorithm is that, at any time, the faults on any seven nodes can be tested to avoid aliasing. So, the groups are formed out of total nodes, in a multiple of seven to carry out the testing of faults. Practical implications -The proposed algorithm is free from the problems of syndromes and utilizes a smaller number of test vectors. Originality/value -Various existing algorithms namely modified counting, walking one's algorithm and others are discussed. A new algorithm is developed which can easily detect board-level dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults. The proposed algorithm is completely free from aliasing and confounding syndromes.

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Design of Run-time signal test architecture in IEEE 1149.1

Kim¹,

Kim²,

Kim³

2010

Journal of the Korea Society of Computer and Information

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IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

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Reconfigurable tester hardware extends JTAG/boundary scan applications while simplifying ate setup

Cited by 3 publications

References 5 publications

A novel method for diagnosis of board level interconnect faults using boundary scan

A novel method for diagnosis of board level interconnect faults using boundary scan

Boundary scan based testing algorithm to detect interconnect faults in printed circuit boards

Design of Run-time signal test architecture in IEEE 1149.1

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