A novel method for diagnosis of board level interconnect faults using boundary scan

Abstract

Over the past years complexity of PCB board and the surface mount technology has increased by leaps and bounds. This limits the use of traditional in-circuit test techniques for testing of such boards. This paper addresses the various issues of board level interconnect testing using Boundary Scan architecture. This work implements BIST using Boundary Scan technique. A new Algorithm is developed to diagnose PCB level faults. The dominant-1 (WOR), dominant-0 (WAND) and stuck-at faults are taken up in this paper. The proposed algorithm is also compared with the existing algorithms viz modified counting, walking one's algorithm and others. Our results are found to be better than the existing algorithms.

New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

“…According to the previous search, there is no test pattern set generated from (7×4) matrix according to the proposal, presented in [7,14]. Therefore, the presented algorithm in this paper generates new test pattern set for m ≥ n to detect interconnect faults between two (three) terminals from seven or ten terminals and to precisely determine its occurrence without the problem of aliasing and confounding syndromes.…”

“…Single-net and multi-net faults are considered the main faults that happens between PCB interconnections. Different algorithms were developed to detect these faults [7,[9][10][11][12][13][14]. They are either shortcircuiting between any two or three wires, denoted as wired-AND (WAND) and wired-OR (WOR) (known bridging faults) or stuck-at faults in a single wire.…”

“…BACKGROUND AND PROBLEM STATEMENT All state-of-the-art algorithms, presented in the literature to detect interconnect faults [7,[9][10][11][12][13][14], can generate the test pattern set that complies with all requirements to detect two short-circuits from seven or ten terminals of integrated circuits (boards). However, they are suffering from different problems either in detection of faults or the implementation of the test pattern set.…”

“…It was proposed in a two-step algorithm with a combination of the MCSA and the Walking One's sequence algorithm, whose disadvantage is high test application time to detect interconnect faults with only two short-circuits in two steps using two different algorithms. The Boundary-scan based testing algorithm (BSBTA) was proposed to test dominant-1 WOR, and dominant-0 WAND between interconnection of two nodes only and stuck-at faults [7,14]. It can diagnose two short-circuit wire only and determine the specific position of target faults with four PTVs only, shown in Table I.…”

“…The BSBTA detects interconnect faults (two short-circuits only) for seven nodes. The authors in [7,14] proposed that, for any node pair, if it is logic '1' at the same bit, this bit position of STVs for both nodes is replaced by the state 'X'. Unfortunately, the BSBTA cannot be properly implemented in the real hardware to replace each state '1' by the state 'X'.…”