New Board-Level Interconnect Fault Diagnosis Approach in Industrial Applications

Abstract

In this paper, the new BIST approach to test interconnect faults, based on the boundary scan architecture, is presented. The new algorithm is implemented by the MATLAB code, whose analysis is based on the random manner to generate the required test pattern set that detects interconnect faults without aliasing and confounding syndromes. The test pattern set complies with all requirements to detect two and three short-circuits from seven and ten terminals of ICs (boards). Different test responses of each short-circuit between different terminals are achieved, considered the basis of the presented fault diagnosis approach. In addition, this paper presents two generative approaches that generate the target test set. It is found that one generative approach using a linear feedback shift-register (LFSR) and a decoder reduces the test application time and suffers from aliasing and confounding syndromes due to the multi-input shift-register (MISR) with high hardware overhead. However, the other generative approach using an LFSR only has large test application time and is not suffering from aliasing and confounding syndromes with low hardware overhead. The new algorithm is compared with several previously published algorithms. The simulation results of the new algorithm have best results comparing to the existing algorithms in terms of the fault coverage and the applicability of the BIST scheme. The new algorithm is the most efficient algorithm to diagnose interconnect faults, based on two and three short-circuits from seven and ten terminals of ICs with accepted test application time and without aliasing and confounding syndromes.