Reconfigurable System-on-Chip design using FPGA

Muralikrishna, B.; Madhumati, G. L.; Khan, Habibulla; Deepika, K. Gnana

doi:10.1109/icdcsyst.2014.6926215

Cited by 8 publications

(5 citation statements)

References 12 publications

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“…To reduce the development time of the program, it is necessary to verify the simulation results of Verilog. After the simulation verification is passed, the wiring of the program and the generation of bitstream files are performed, downloading the generated bitstream files to the FPGA development board for board testing [12]. During the research process, Vivado software was used to simulate and verify the software part of this system.…”

Section: Simulationmentioning

confidence: 99%

Design and Implementation of DDS Signal Generator Based on FPGA

2024

AJST

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With the rapid development of semiconductor technology, the digital circuit of the control chip gradually replaces the analog circuit of the traditional signal generator, which improves the performance of the signal generator and reduces the cost of research, development and production. This paper proposes a design scheme that takes FPGA chip as the control center. The signal generator system mainly includes DAC module, FPGA module and key module. The system uses Verilog language to develop the sine wave digital signal generation and key switching frequency control logic circuit on FPGA. The frequency control word circuit in the FPGA module provides multiple frequency sine wave selection, and the look-up table circuit realizes the reading of different phases by controlling the read address of the ROM. The 14-bit high-speed DAC module converts the digital signals sent by FPGA into analog signals. The DAC module integrates low-pass filter processing to increase the smoothness of the signal. After testing, the system meets the design requirements.

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Section: Simulationmentioning

confidence: 99%

Design and Implementation of DDS Signal Generator Based on FPGA

2024

AJST

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“…2. It is based on the self-configuration of SOPC supported by FPGA and the FPGA is partitioned into the static and dynamic region [3] . The static region will keep the working status unchanged and the dynamic region will be reconfigured when the running FPGA is reconfigured.…”

Section: A the Local Reconfigurationmentioning

confidence: 99%

Research on reconfiguration technology based on SOPC for PXI instrument

Zhao

Hou

Wang

2015

2015 Ieee Autotestcon

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The traditional PXI instrument generally has fixed function and its firmware is difficult to upgrade. To overcome this problem, the reconfigurable PXI instrument is proposed to meet different requirements. The design is implemented by using Field Programmable Gate Arrays (FPGAs) with reconfigurable function. In this paper, in order to satisfy the different vehicle bus test requirements, a reconfigurable serial communication module is designed, and the serial communication interface and protocol of this module can be reconfigured dynamically. The design is based on Dynamic Partial Reconfiguration (DPR) which is implemented by the Xilinx Virtex-5 FPGA supporting the System on Programmable Chip (SOPC). As a character, online reconfiguration of local and remote is supported. The test results indicate that 5 different protocols are supported. In the meantime, the design is also with the character of real-time. When the configuration data is 167310 Bytes, the time of local reconfiguration is less than 5ms and the remote reconfiguration is accomplished within 70ms.

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“…The module can be interfaced with the FPGA module through headers available on training board, serial (RS-232) interface and RS-485 interface [4]. In this practical scenario, MHX-2400 has been interfaced with Spartan 3E using header available on starter kit.…”

Section: Integration Of Telecontrol Interfacementioning

confidence: 99%

Benchmarking of Data Communication Protocol for Integration of Telecontrol Interface with RTU

Aamir¹,

Khan²,

Chowdhry³

2015

SSURJ

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The outcome of this research work is focused onoptimized the design of wireless link for an FPGA based RemoteTerminal Unit (RTU). A situation representing multiple RTUscommunicating with one Telecontrol Interface (TCI) developedto address optimized implementation of wireless SCADA. It wasthen further verified by means of benchmarking. The hardwareimplementation and verification of this particular RTU designhas been done using a starter kit based on XILINX Spartan-3Series FPGA with 500K logic gates and MHX-2400 frequencyhopping2.4 GHz spread-spectrum communications modulewhich is used as Telecontrol Interface. The FPGA based RTU isflexible in terms of I/Os, CPU and radio related configurationsand any expansion in design can be accommodated quickly ifneeded as FPGA based designs are reconfigurable. However, theintegration of MHX-2400 had been examined and found suitableas Telecontrol Interface for this development.

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Reconfigurable System-on-Chip design using FPGA

Cited by 8 publications

References 12 publications

Design and Implementation of DDS Signal Generator Based on FPGA

Design and Implementation of DDS Signal Generator Based on FPGA

Research on reconfiguration technology based on SOPC for PXI instrument

Benchmarking of Data Communication Protocol for Integration of Telecontrol Interface with RTU

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