Reconfigurable quadruple quantum dots in a silicon nanowire transistor

Abstract

We present a novel reconfigurable metal-oxide-semiconductor multi-gate transistor that can host a quadruple quantum dot in silicon. The device consist of an industrial quadruple-gate silicon nanowire field-effect transistor. Exploiting the corner effect, we study the versatility of the structure in the single quantum dot and the serial double quantum dot regimes and extract the relevant capacitance parameters. We address the fabrication variability of the quadruple-gate approach which, paired with improved silicon fabrication techniques, makes the corner state quantum dot approach a promising candidate for a scalable quantum information architecture.Semiconductor quantum bits relying on the charge or spin degree of freedom of a single electron, bound to a quantum dot (QD) or impurity atom, are considered promising candidates for the base elements of solid state quantum computing architectures [1]. Building a successful quantum computer, however, requires a scalable multi-qubit approach to implement the necessary algorithms [2]. Electron spins bound to silicon QDs are seen as promising candidates for this due to their long coherence time, electrical tunability and flexible coupling geometries [3][4][5]. A further advantage of using Si is the possibility to integrate with current complementary-metaloxide-semiconductor (CMOS) technology [5-8] and leverage its established industrial platform for large scale circuits. Recently, the integration of Si quantum dots and double quantum dots (DQD) into CMOS technology has been taken a step further with reports of fewelectron QDs, DQDs, and donor-QD hybrids created within industry-standard Si nanowire transistors [9][10][11][12]. Combined with a gate-based readout scheme that alleviates the need for a separate charge sensor [10-14] these approaches pave the way towards a large scale quantum computing architecture based on current CMOS technology.In this Letter, we report on a reconfigurable QD and DQD system in a quadruple-gate CMOS transistor. It incorporates one, or a pair, of CMOS corner state quantum dots [10,11] in a variety of configurations. Each of the four gates can host an independently tunable quantum dot created in the square channel by electrostatic enhancement and confinement resulting from the topgate electrodes and accompanying silicon nitride spacers. We characterise one exemplary single QD and demonstrate that different DQD configurations can be set at will. Building on previous demonstrations [10][11][12] results provide a way to scale up CMOS quantum information architectures and to create reconfigurable silicon multi-dot arrangements. The device presented here is a fully depleted silicon-oninsulator (FDSOI) nanowire field-effect transistor with four independently addressable top-gates. The polyarXiv:1603.03636v1 [cond-mat.mes-hall]

A silicon-based single-electron interferometer coupled to a fermionic sea

“…The full fabrication details can be found elsewhere [32]. In square-section nanowire transistors, electron accumulation happens first at the top-most corners of the transistor creating a double quantum dot (DQD) in parallel with the source and drain ohmic contacts as can be seen in the schematics in Fig.1(b) [29,33]. Measurements are performed at the base temperature of a dilution refrigerator (35 mK) using gate-based radiofrequency reflectometry as in Ref.…”

Single-electron operations in a foundry-fabricated array of quantum dots

“…In gallium arsenide, 2D arrays recently allowed coherent spin operations and quantum simulations 7 , 8 . In silicon, 2D arrays have been limited to transport measurements in the many-electron regime 9 .…”

Charge Detection in an Array of CMOS Quantum Dots

“…However, these demonstrations were achieved in GaAs heterostructures where the hyperfine interaction limits the coherence time to a few tens of nanoseconds. To create functional quantum-dot arrays on a more-scalable platform, such as silicon quantum dots [15][16][17][18], the same level of control and addressability needs to be achieved.…”