Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing

Abstract

With the scaling of technology, the industry is experiencing a shift from multi-core to many-core architectures. However, traditional on-chip metallic interconnects may not scale to support these many-core architectures due to the increased hop count, high power dissipation, and increased latency. Recently, attention has recently been shifted to emerging technologies such as optical and wireless interconnects for future on-chip communications. Although emerging technologies show promising results for power-e cient, low-latency, and scalable on-chip interconnects, the use of single technology may not be su cient to support future many-core architectures. In this paper, we propose a Reconfigurable Optical-Wireless Network-on-Chip (R-OWN) that facilitates communication through static optical links and reconfigurable wireless links. The network diameter of R-OWN is restricted to three hops by dividing the network into several optical domains of 64-cores (called a cluster) and by connecting the clusters using one-hop wireless network. The optical bandwidth is e ciently shared using time division multiplexing (TDM), and the wireless bandwidth is shared using frequency division multiplexing (FDM). Packets routed across optical and wireless networks are proved to be deadlock-free. Our results indicate that R-OWN improves energy-e ciency by 44-51%, performance (throughput and latency) by 13-31%, and area by 4-13% when compared to state-of-the-art wired, wireless, optical, and hybrid on-chip networks.

Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios

“…For NoC architectures, hybrid interconnects are more suitable designs to improve throughput, power consumption, and scalability than using only one interconnect type. This premise is demonstrated in WiNoC state-of-the-art where several approaches combine wired/wireless and optical/wireless [16] solutions. Combining wireless links with another interconnect solution allows for the number of embedded cores to be easily scaled and latency and power to be improved.…”