Reconfigurable Model-Based Test Program Generator for Microprocessors

Kamkin, Alexander; Корныхин, Е.В.; Vorobyev, Dmitry

doi:10.1109/icstw.2011.35

Cited by 12 publications

(6 citation statements)

References 9 publications

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“…The first version of the prototype was tried with several industrial microprocessors and their subsystems. The experimental results are provided in the work of Kamkin, Kornykhin and Vorobyev [4]. Our current plans are to develop a full featured product that could be used by microprocessor vendors.…”

Section: Discussionmentioning

confidence: 99%

“…Finally, it should be said that Institute for System Programming of RAS (ISPRAS) has already done some research and development on the TPG topic [4] [7]. The present article summarizes the ideas that have been accumulated in ISPRAS and provides an overview of the research project our team is working on at the moment.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…For each instruction of the TT the tool formulates a constraint satisfaction problem (CSP) and generates test data by solving the CSP. A known disadvantage of Genesys-Pro is that it is difficult to model instructions affecting memory devices [4]. Therefore, there are reasons to think that Genesys-Pro is hardly reconfigurable if significant modifications of the memory devices are required.…”

Section: Related Work and Motivationmentioning

confidence: 99%

“…So, buffer configuration information includes the following attributes: set size (associativity), number of sets, line field description, address-to-index translation rule, rule for checking if a line and an address match and data displacement policy. To specify this information, we use CFs of the following kind [4] Another important aspect related to architectural models is dependencies between instructions. Instructions change the state of the microprocessor and, thus, affect the behavior of subsequent instructions.…”

Section: Microtesk Overviewmentioning

confidence: 99%

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MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

Kamkin¹,

Tatarnikov²

2012

Proceedings of the Spring/Summer Young Researchers' Colloquium on Software Engineering

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Abstract-Test program generation plays a major role in functional verification of microprocessors. Due to tremendous growth in complexity of modern designs and rigid constraints on time to market, it becomes an increasingly difficult task. In spite of powerful test program generators available in the market, development of functional tests is still known to be the bottleneck of the microprocessor design cycle. The common problem is that it takes significant effort to reconfigure a test program generation tool for a new microprocessor design. The modelbased approach applied in the state-of-the-art tools, like GenesysPro, still does not provide enough flexibility since creating a microprocessor model is difficult and requires special knowledge and skills. The article suggests an approach to ease generator customization by using architecture specifications that describe the microprocessor behavior at a higher level. The approach is aimed at facilitating development of architecture models and, thus, minimizing time required to create functional tests. At the moment, we are working to implement a new generation of the test program generator MicroTESK that can be easily configured for various microprocessor architectures.

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Section: Discussionmentioning

confidence: 99%

Section: Related Work and Motivationmentioning

confidence: 99%

Section: Related Work and Motivationmentioning

confidence: 99%

Section: Microtesk Overviewmentioning

confidence: 99%

See 2 more Smart Citations

MicroTESK: An ADL-Based Reconfigurable Test Program Generator for Microprocessors

Kamkin¹,

Tatarnikov²

2012

Proceedings of the Spring/Summer Young Researchers' Colloquium on Software Engineering

Self Cite

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“…To reduce number of tests, one can use heuristics, like operation factorization, limitation of the number of dependencies, etc. [7] V. TOOL SUPPORT The suggested approach to specification and test sequence generation is supported by the CTESK toolkit developed at the Institute for System Programming of the Russian Academy of Sciences (ISPRAS) [9]. This toolkit is originally intended for testing software systems written in C, but it has been adapted for verification of hardware designs.…”

Section: Operation-driven Modelsmentioning

confidence: 99%

Contract Specifiaction of Hardware Designs at Different Abstraction Levels: Application to Functional Verification

Chupilko¹,

Kamkin²

2010

Proceedings of the Spring/Summer Young Researchers' Colloquium on Software Engineering

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The paper touches upon the issues of functional specification and verification of digital hardware at different abstraction levels. It shows how behavioral models of various degrees of abstraction can be represented by means of the contract paradigm and how contract specifications can be applied to generate test sequences in an automated way. The testing technique under consideration is based on the traversal of FSM derived from specifications. Taking into account that contract specifications are well known to be a high-efficient tool for constructing response checkers and estimating test coverage, we can assuredly report that the contract-based approach is a universal solution for hardware verification at different levels of abstraction.

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