Test Program Generation for a Microprocessor

Brucker, Achim D.; Feliachi, Abderrahmane; Nemouchi, Yakoub; Wolff, Burkhart

doi:10.1007/978-3-642-38916-0_5

Cited by 6 publications

(7 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Homogeneous relations, where the input and output alphabets belong to the same state space. An example of such a relation is the set of state transitions over the Instruction Set Architecture (ISA) instructions of a microprocessor [4]. In the theory of alphabetized relational calculus, for the case of partial correctness of imperative programs, the healthiness conditions are the identity function.…”

Section: Utpmentioning

confidence: 99%

“…In our work we use SP, or forward, reasoning [14]. The notation e «v»/x means that «v» is substituted for x in e. This rule is referred to as the Floyd assignment rule [14] after Robert W. Floyd, and it is easy to express in our setting as Isabelle/UTP has a substitution theory 4 . Namely, reasoning on assignment boils down to reasoning on substitutions.…”

Section: Forward Reasoning In Isabelle/utpmentioning

confidence: 99%

See 1 more Smart Citation

Using Isabelle/UTP for the Verification of Sorting Algorithms: A Case Study

Bockenek¹,

Lammich²,

Nemouchi³

et al. 2019

EasyChair Preprints

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Utpmentioning

confidence: 99%

Section: Forward Reasoning In Isabelle/utpmentioning

confidence: 99%

Using Isabelle/UTP for the Verification of Sorting Algorithms: A Case Study

Bockenek¹,

Lammich²,

Nemouchi³

et al. 2019

EasyChair Preprints

Self Cite

View full text Add to dashboard Cite

show abstract

“…IO-Determinism and Non-IO-Determinism adding some notion of time), but most practical approaches do assume it as we do throughout this paper. There are approaches (including our own [3]) that allow at least a limited form of access to the final (internal) state of the SUT.…”

Section: A Guided Tour On Automata Notions For Testingmentioning

confidence: 99%

“…In the former "truly non-deterministic" case step can and will at run-time choose different results, the latter "under-specified deterministic" version will decide in a given model always the same way: a choice that is, however, unknown at specification level and only declaratively described via post. For many systems (like system scheduler [4], processor models [3], etc.) it was possible to opt for an under-specified deterministic stepping function.…”

Section: Formal Presentations Of Automata: the Monadic Approachmentioning

confidence: 99%

Monadic Sequence Testing and Explicit Test-Refinements

Brucker

Wolff²

2016

Tests and Proofs

Self Cite

View full text Add to dashboard Cite

We present an abstract framework for sequence testing that is implemented in Isabelle/HOL-TestGen. Our framework is based on the theory of state-exception monads, explicitly modelled in HOL, and can cope with typed input and output, interleaving executions including abort, and synchronisation. The framework is particularly geared towards symbolic execution and has proven effective in several large case-studies involving system models based on large (or infinite) state. On this basis, we rephrase the concept of test-refinements for inclusion, deadlock and IOCO-like tests, together with a formal theory of its relation to traditional, IO-automata based notions.

show abstract

“…These were measured on a dual-core 8GB Intel Core i5-3320M using a development version of HOL4 from March 2014 running on PolyML 5.5.1. The generated HOL and SML for the M0 model and tools is present in the HOL4 distribution 4 . An STM32F0-Discovery board was used as the target.…”

Section: Performancementioning

confidence: 99%

Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation

Campbell

Stark

2014

Formal Methods for Industrial Critical Systems

View full text Add to dashboard Cite

We validate a HOL4 model of the ARM Cortex-M0 microcontroller core by testing the model's behaviour on randomly chosen instructions against a real chip. The model and our intended application involve precise timing information about instruction execution, but the implementations are pipelined, so checking the behaviour of single instructions would not give us sufficient confidence in the model. Thus we test the model using sequences of randomly chosen instructions. The main challenge is to meet the constraints on the initial and intermediate execution states: we must ensure that memory accesses are in range and that we respect restrictions on the instructions. By careful transformation of these constraints an off-the-shelf SMT solver can be used to find suitable states for executing test sequences.

show abstract

Test Program Generation for a Microprocessor

Cited by 6 publications

References 18 publications

Using Isabelle/UTP for the Verification of Sorting Algorithms: A Case Study

Using Isabelle/UTP for the Verification of Sorting Algorithms: A Case Study

Monadic Sequence Testing and Explicit Test-Refinements

Randomised Testing of a Microprocessor Model Using SMT-Solver State Generation

Contact Info

Product

Resources

About