Reconfigurable hardware for efficient implementation of programmable FIR filters

Denk, T.C.; Nicol, Chris; Larsson, Patrik; Azadet, K.

doi:10.1109/icassp.1998.678158

Cited by 7 publications

(1 citation statement)

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“…As seen in Eq. (1), the FIR filter offers a high regularity to enable that the hardware can be folded to reduce the hardware complexity of the FIR architecture [1][2][3]. Such folding approach can be classified into input-data folding, coefficient folding and tap folding [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

A Low-Power Folded Programmable FIR Architecture

Chen

2006

2006 IEEE Workshop on Signal Processing Systems Design and Implementation

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Based on the radix-4 Booth algorithm, a scheme that integrates tap folding and coefficient folding is proposed to design a programmable Finite Impulse Response (FIR) architecture with low power dissipation. In addition, without increasing hardware complexity and degrading computational performance, the effective selection on input data is realized to lower the operating frequencies of the latches and multiplexers involved with the input data. With the reduction on the frequency of the input data being selected to the Booth decoders, the power consumed in the Booth decoders can be also minimized. The proposed and conventional FIR architectures are implemented using the TSMC 0.1 8,tm CMOS technology. The areas and power consumption of these architectures are analyzed and compared. Under the same specifications and throughput rate, the results revealed that in comparison to the conventional architectures, the proposed FIR architecture not only saves about 18.18% to 39.19% of area occupied, it also reduces 14.23% to 25.56% in power consumption.

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