Reconfigurable content-based router using hardware-accelerated language parser

Abstract

This article presents a dense logic design for matching multiple regular expressions with a field programmable gate array (FPGA) at 10+ Gbps. It leverages on the design techniques that enforce the shortest critical path on most FPGA architectures while optimizing the circuit size. The architecture is capable of supporting a maximum throughput of 12.90 Gbps on a Xilinx Virtex 4 LX200 and its performance is linearly scalable with size. Additionally, this article presents techniques for parsing data streams to provide semantic information for patterns found within a data stream. We illustrate how a content-based router can be implemented with our parsing techniques using an XML parser as an example. The content-based router presented was designed, implemented, and tested in a Xilinx Virtex XCV2000E FPGA on the FPX platform. It is capable of processing 32-bits of data per clock cycle and runs at 100 MHz. This allows the system to process and route XML messages at 3.2 Gbps.

A Flexible SoC and Its Methodology for Parser-Based Applications

“…For instance, in [Lunteren et al 2004;Dai et al 2010], a specific architecture was proposed to speed-up the eXtensible Markup Language (XML) document parsing. Similarly, in [Moscola et al 2008], an FPGA based regular expression language is used to parse XML based streams. These works have demonstrated that FPGAs offer a viable alternative thanks to their power efficiency as well as their higher throughput when compared with software implementation.…”

Improving the performance of message parsers for embedded systems

“…Hence, high-level specifications of network protocol messages are mapped directly into hardware description languages such as VHDL to be then successively synthesized into ASIC or FPGA [17,18,19]. However, hardware parsers are provided as is and require strong understanding of hardware design fundamentals to integrate them with network programming applications.…”

Zebra: Building Efficient Network Message Parsers for Embedded Systems

“…Hence, high-level specifications of network protocol messages are mapped directly into hardware description languages such as VHDL to be then successively synthesized into ASIC or FPGA [12], [13], [14]. However, hardware parsers are provided as is and require strong understanding of hardware design fundamentals to integrate them with network programming applications.…”