Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Wang, Kang; Zhang, Liuyang; Klein, Jacques-Olivier; Zhang, Youguang; Ravelosona, D.; Zhao, Weisheng

doi:10.1109/ted.2015.2412960

Cited by 139 publications

(6 citation statements)

References 41 publications

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“…5(b)], as detailed in the following. Even though process variability is of great importance for the STT-MRAM design [27], we did not take into account such effects given the relatively low deviceto-device variation of conduction and switching among our samples. The observed variation in cycling endurance for a given voltage might result from intrinsic variability of both the position in the oxide layer and the number of generated defects.…”

Section: Endurance Modelmentioning

confidence: 99%

Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Carboni

Ambrogio

Chen

et al. 2018

IEEE Trans. Electron Devices

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Perpendicular spin-transfer torque (p-STT) magnetic memory is gaining increasing interest as a candidate for storage-class memory, embedded memory, and possible replacement of static/dynamic memory. All these applications require extended cycling endurance, which should be based on a solid understanding and accurate modeling of the endurance failure mechanisms in the p-STT device. This paper addresses cycling endurance of p-STT memory under pulsed electrical switching. We show that endurance is limited by the dielectric breakdown of the magnetic tunnel junction stack, and we model endurance lifetime by the physical mechanisms leading to dielectric breakdown. The model predicts STT endurance as a function of applied voltage, pulsewidth, pulse polarity, and delay time between applied pulses. The dependence of the endurance on sample area is finally discussed. Index Terms-Cycling endurance, magnetic tunnel junction (MTJ), reliability analysis, reliability modeling, spintransfer torque magnetoresistive RAM (STT-MRAM). I. INTRODUCTION M AGNETORESISTIVE random access memory (MRAM) is one of the most promising memory technology due to its fast switching, nonvolatile states, high endurance, CMOS compatibility, and low current operation [1]. Thanks to these characteristics, MRAM is under intense consideration for applications as storageclass memory (SCM) [2]-[5] and embedded nonvolatile

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Section: Endurance Modelmentioning

confidence: 99%

Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Carboni

Ambrogio

Chen

et al. 2018

IEEE Trans. Electron Devices

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show abstract

“…There are mainly four soft failure sources [17,83,84,85], including write failure due to the intrinsic stochastic STT-driven MTJ switching mechanism, retention failure due to limited thermal stability, radiation effects, and read disturbances due to the large read currents for enough sensing margin. Correspondingly, researchers have proposed techniques to tolerate these failures.…”

Section: Failure Tolerant Design Techniquesmentioning

confidence: 99%

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

et al. 2016

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Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.

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“…In recent years, many STT-MRAM circuits have been prototyped on technology scale down nodes [7,8,9,10]. However, with technology scaling down, there are some critical issues associated with the sensing circuits of STT-MRAM because the combination of STT with MTJ suffers from both intrinsic stochastic switching behaviors and a high sensitivity to process variations [11,12,13,14,15,16]. In addition, the effect of a negative bias temperature instability (NBTI) on a pMOS device in the sensing circuits of RAM becomes an important factor affecting the speed of a pMOS device and the mismatch of the sensing circuits [17,18].…”

Section: Introductionmentioning

confidence: 99%

A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

Zhang

Liu

Zhang

et al. 2019

IEICE Electron. Express

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STT-MRAM has been considered to be one of the most promising non-volatile memory candidates due its non-volatility, high speed, and unlimited endurance etc. However, with technology scaling down, STT-MRAM suffers from high sensitivity to process voltage and temperature (PVT) variations. Additionally, the negative bias temperature instability (NBTI) effect has become an important factor affecting the life of the pMOSFETs used in an STT-MRAM sense amplifier. Therefore, designing a more reliable sense amplifier has become a critical challenge. In this paper, a novel architecture for a sense amplifier is proposed, which includes switching transistors to decrease the NBTI effect on the pMOS device, and a balanced transistor to decrease the sensitivity of the sense amplifier to process variations.

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Reconfigurable Codesign of STT-MRAM Under Process Variations in Deeply Scaled Technology

Cited by 139 publications

References 41 publications

Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy

A novel sense amplifier to mitigate the impact of NBTI and PVT variations for STT-MRAM

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