Modeling of Breakdown-Limited Endurance in Spin-Transfer Torque Magnetic Memory Under Pulsed Cycling Regime

Abstract

Perpendicular spin-transfer torque (p-STT) magnetic memory is gaining increasing interest as a candidate for storage-class memory, embedded memory, and possible replacement of static/dynamic memory. All these applications require extended cycling endurance, which should be based on a solid understanding and accurate modeling of the endurance failure mechanisms in the p-STT device. This paper addresses cycling endurance of p-STT memory under pulsed electrical switching. We show that endurance is limited by the dielectric breakdown of the magnetic tunnel junction stack, and we model endurance lifetime by the physical mechanisms leading to dielectric breakdown. The model predicts STT endurance as a function of applied voltage, pulsewidth, pulse polarity, and delay time between applied pulses. The dependence of the endurance on sample area is finally discussed. Index Terms-Cycling endurance, magnetic tunnel junction (MTJ), reliability analysis, reliability modeling, spintransfer torque magnetoresistive RAM (STT-MRAM). I. INTRODUCTION M AGNETORESISTIVE random access memory (MRAM) is one of the most promising memory technology due to its fast switching, nonvolatile states, high endurance, CMOS compatibility, and low current operation [1]. Thanks to these characteristics, MRAM is under intense consideration for applications as storageclass memory (SCM) [2]-[5] and embedded nonvolatile

Stochastic Memory Devices for Security and Computing

“…Switching between the two states takes place either by the direct application of a magnetic field in Toggle-MRAM [94] or by the spin-transfer torque (STT) effect, which was theoretically predicted [95,96] and later experimentally demonstrated. [105] Perpendicular STT magnetic memories are gaining considerable interest due to their fast switching, [106] nonvolatile states, high endurance, [107] CMOS compatibility, and low current operation. [100] Interest in the STT-MRAM has considerably increased after the demonstration of perpendicular spin-transfer torque (p-STT), where the magnetic polarization of the two FM layers is perpendicular to the MTJ plane, thus allowing a reduced switching current at equal retention time, hence lower power and improved scalability [101,102] with respect to the in-plane concept (i-STT).…”

“…[107] To improve the cycling reliability and achieve virtually unlimited endurance, the spin-orbit torque (SOT) MRAM has been proposed. [107] To improve the cycling reliability and achieve virtually unlimited endurance, the spin-orbit torque (SOT) MRAM has been proposed.…”

“…[100] As a result, the FL magnetic state is stable at room temperature, and can switch to the opposite magnetization only under an external perturbation, such as a current pulse for STT-MRAM. [107] The resistance changes with time by random abrupt transitions between the two resistance levels, corresponding to the two stable magnetic states of the FL. [21] As a result, the FL magnetization spontaneously switches between the two stable states due to the enhanced sensitivity to thermal fluctuations.…”

“…The relative change of the measured resistance is called tunnel magnetoresistance (TMR) and is typically around 200% for state‐of‐the‐art MTJ . Perpendicular STT magnetic memories are gaining considerable interest due to their fast switching, nonvolatile states, high endurance, CMOS compatibility, and low current operation . Note that magnetization switching in MTJ depends on the interaction of the FL with random thermal fluctuations, thus STT‐MRAM set/reset processes are inherently affected by stochastic variations .…”

“…Endurance in STT‐MRAM devices is generally limited by the dielectric breakdown of the tunnel layer, as a result of the repeated pulses inducing an electrical stress and a consequent degradation . To improve the cycling reliability and achieve virtually unlimited endurance, the spin‐orbit torque (SOT) MRAM has been proposed.…”