Recombination dynamics of traps in SiO 2 layer on Si by scanning capacitance microscopy

Abstract

The depth-dependent carrier density and trapped charges in an arsenic-implanted silicon sample were measured by using scanning capacitance microscopy (SCM). The position-dependent capacitance versus voltage scans were measured at various dc bias voltages. A strong dc bias dependence was observed at the interface of an abrupt junction between n + and p. The bias-dependent SCM images were used to follow the recombination dynamics of traps. The results show good agreement with quasi-three-dimensional simulations, suggesting that they can be used to map device structure.With the recent developments in silicon submicrometer technology, the characterization of the three-dimensional carrier density profile in a device has become one of the most important issues. In a sub-micron device, it is very difficult to directly measure the carrier density profile around the gate because many tools measure only the profile averaged over a large area. Secondary ion mass spectrometry (SIMS) and spreading resistance profilometry (SRP) have widely been used to measure dopant profiles. The tomographic approach [1] and the angle lapping technique [2] have been developed to measure two-dimensional profiles with improved resolution. Recently, nano-SRP, utilizing scanning probe microscopy, has further improved spatial resolution [3][4][5]. Other important problems in submicron MOS devices are device failure and noise from hot electron effects and trapped charges. If the gate oxide in a MOS device becomes thinner than 10 nm and 5 V is still applied to the gate, problems related to the hot electron effect and trapped charges become more serious. At present there is no tool to measure the local defects such as trapped charges and the defects created by hot electrons. When data is taken by macroscopic measuring tools and then compared with the simulated results poor agreement is found.Since the advent of the scanning tunneling microscope (STM) and the atomic force microscope (AFM), geometrical and electrical measurements of a semiconductor surface have become possible with atomic resolution. As a probe is scanned over a specific area, the carrier density profile [6], the potential across abrupt junctions [7], the impurity distribution [8], and the carrier scattering near defect centers [9] can be measured at the same time. The carrier density of a semiconductor can be mapped by the capacitance-voltage (C-V ) dependence, and the geometrical structure can be measured by STM or AFM. In order to have good spatial resolution, the sensitivity of the detector has to be better than 10 −19 F [10]. This can be achieved with the scanning capacitance microscope (SCM) operating under ambient conditions by using a sample with only a capping oxide and without any further extensive sample preparation. However, it only measures the carrier density rather than the dopant concentration of the semiconductor surface. If the dopant density does not vary abruptly within a few Debye lengths, it can be estimated from the measured C-V dependence [11]. In an earlier SCM...

Charge storage in silicon-implanted silicondioxide layers examined by scanning probe microscopy

“…They examined metal-nitride-oxide-semiconductor structures, where the trapping takes place in the siliconnitride layer, well separated from the injecting electrode by a tunneling oxide. During the past years several papers on the SCM characterization of local charging effects in thin SiO 2 layers appeared [26][27][28][29]. Local write/erase charge transitions, stimulated by changes of the tip dc bias, were used to determine parameters such as the time constants or the threshold bias for the trapping and detrapping of carriers in the silicondioxide.…”