Realization of Delayed Cellular Neural Network model ON FPGA

Karakaya, Barış; Çelik, Vedat; Gülten, Arif

doi:10.1109/ebbt.2018.8391449

Cited by 4 publications

(2 citation statements)

References 14 publications

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“…Figure 11c shows the execution time in seconds for various methods that used chaotic maps to implement pseudorandom number generators. Karakaya et al [70] have achieved the highest operating frequency of 59.492 MHz with 165 registers, 311 FPGA resources, and 22 multipliers, which was the lowest number of hardware resources used in the reported literature. Hamza et al [30] achieved the lowest execution time of 0.23 seconds while using a 2D Zaslavsky chaotic map for image encryption.…”

Section: Methodsmentioning

confidence: 97%

A Review on Applications of Chaotic Maps in Pseudo-Random Number Generators and Encryption

Naik

Singh

2022

Ann. Data. Sci.

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Because of the COVID-19 pandemic, most of the tasks have shifted to an online platform. Sectors such as e-commerce, sensitive multi-media transfer, online banking have skyrocketed. Because of this, there is an urgent need to develop highly secure algorithms which can not be hacked into by unauthorized users. The method which is the backbone for building encryption algorithms is the pseudo-random number generator based on chaotic maps. Chaotic maps are mathematical functions that generate a highly arbitrary pattern based on the initial seed value. This manuscript gives a summary of how the chaotic maps are used to generate pseudo-random numbers and perform multimedia encryption. After carefully analyzing all the recent literature, we found that the lowest correlation coefficient was 0.00006, which was achieved by Ikeda chaotic map. The highest entropy was 7.999995 bits per byte using the quantum chaotic map. The lowest execution time observed was 0.23 seconds with the Zaslavsky chaotic map and the highest data rate was 15.367 Mbits per second using a hyperchaotic map. Chaotic map-based pseudo-random number generation can be utilized in multi-media encryption, video-game animations, digital marketing, chaotic system simulation, chaotic missile systems, and other applications.

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Section: Methodsmentioning

confidence: 97%

A Review on Applications of Chaotic Maps in Pseudo-Random Number Generators and Encryption

Naik

Singh

2022

Ann. Data. Sci.

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“…Onboard systems for NN cryptographic protection of data must have variable hardware for rapid changes in NN architecture. The use of modern element base (microcontrollers, programmable logic integrated circuits FPGA) in the development of onboard and embedded systems makes it possible to reduce their weight, size, and power consumption [26,27] and, in the development of onboard systems of NN cryptographic, data protection provides a quick change of encryption and decryption keys.…”

Section: Introductionmentioning

confidence: 99%

An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV

Tsmots

Teslyuk

Łukaszewicz

et al. 2023

Drones

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An approach to the implementation of a neural network for real-time cryptographic data protection with symmetric keys oriented on embedded systems is presented. This approach is valuable, especially for onboard communication systems in unmanned aerial vehicles (UAV), because of its suitability for hardware implementation. In this study, we evaluate the possibility of building such a system in hardware implementation at FPGA. Onboard implementation-oriented information technology of real-time neuro-like cryptographic data protection with symmetric keys (masking codes, neural network architecture, and matrix of weighting coefficients) has been developed. Due to the pre-calculation of matrices of weighting coefficients and tables of macro-partial products and the use of tabular-algorithmic implementation of neuro-like elements and dynamic change of keys, it provides increased cryptographic stability and hardware–software implementation on FPGA. The table-algorithmic method of calculating the scalar product has been improved. By bringing the weighting coefficients to the greatest common order, pre-computing the tables of macro-partial products, and using operations of memory read, fixed-point addition, and shift operations instead of floating-point multiplication and addition operations, it provides a reduction in hardware costs for its implementation and calculation time as well. Using a processor core supplemented with specialized hardware modules for calculating the scalar product, a system of neural network cryptographic data protection in real-time has been developed, which, due to the combination of universal and specialized approaches, software, and hardware, ensures the effective implementation of neuro-like algorithms for cryptographic encryption and decryption of data in real-time. The specialized hardware for neural network cryptographic data encryption was developed using VHDL for equipment programming in the Quartus II development environment ver. 13.1 and the appropriate libraries and implemented on the basis of the FPGA EP3C16F484C6 Cyclone III family, and it requires 3053 logic elements and 745 registers. The execution time of exclusively software realization of NN cryptographic data encryption procedure using a NanoPi Duo microcomputer based on the Allwinner Cortex-A7 H2+ SoC was about 20 ms. The hardware–software implementation of the encryption, taking into account the pre-calculations and settings, requires about 1 msec, including hardware encryption on the FPGA of four 2-bit inputs, which is performed in 160 nanoseconds.

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Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption

Hagras

Saber

2020

Multimed Tools Appl

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Realization of Delayed Cellular Neural Network model ON FPGA

Cited by 4 publications

References 14 publications

A Review on Applications of Chaotic Maps in Pseudo-Random Number Generators and Encryption

A Review on Applications of Chaotic Maps in Pseudo-Random Number Generators and Encryption

An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV

Low power and high-speed FPGA implementation for 4D memristor chaotic system for image encryption

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