Real-time Traffic Sign detection and Recognition on FPGA

Abstract

In this thesis, an embedded system for traffic sign detection and recognition is proposed. Proposed system is first designed in MATLAB and optimized. After optimization process, system design is transferred to FPGA and Virtex-V FX70 FPGA is selected for implementation platform. 640x480 sized image in RGB format is sent to FPGA system via computer interface. This image is segmented for red, blue, and yellow colors. Red and blue color maps are divided into 8x8 sub-blocks. Yellow color map is divided into 32x32 sub-blocks. After that, blocks which have more than 30 % valid pixels are marked as valid. Red and blue maps are converted into 80x60 and blobs are detected in these maps. Size of the detected blob is examined first and appropriate sized regions are marked as valid. Next, to be marked as traffic sign, valid regions are expected to meet one of the three conditions: Vertical neighboring, yellow sign neighboring and pole detection below the region. Regions marked as traffic sign are interpolated to 60x60. Color segmentation operation is applied to these regions and edges are extracted in segmented images. Hough Transform is applied to edge images and contour information is extracted. Finally, Informative Pixel Percentage (IPP) operation is applied to inner region of the signs and results are obtained. FPGA system is composed of two sub-parts: Processor system and hardware (logic) system. Color segmentation, region detection and pole detection modules are implemented in hardware system. Rest of the operations is implemented in the processor system. To test success of the implemented system, 137 images, which include 162 traffic signs, are sent to this system and 90.1 % detection and 90.4 % recognition rates are achieved.