Real-Time Software Implementation of H.264 Baseline Profile Video Encoder for Mobile and Handheld Devices

Rao, G. Nageswara; Prasad, R.S.V.; Chandra, D.; Narayanan, S.

doi:10.1109/icassp.2006.1661311

Cited by 9 publications

(6 citation statements)

References 5 publications

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“…Software components are characterized by the allotted time for their real-time performance and the corresponding processor clock frequency. In this simulation, we use the same values as the optimized software implementation of the H.264/AVC encoder proposed in [21] as presented in Table 4.…”

Section: Simulation Resultsmentioning

confidence: 99%

Power aware mapping of an RVC encoder on a many-core platform

Moghadas

Hashemi

2011

2011 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB)

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In this paper, a power aware mapping of a reconfigurable video coding (RVC) representation of an H.264/AVC encoder on a heterogeneous many-core platform has been presented. Through this example the benefits of using RVC for flexible and future proof implementations has been highlighted. Furthermore, the low cost modeling of the power efficient mapping algorithm enables dynamic mapping of applications on many-core platforms where power is a concern. Preliminary results indicate that the mapped encoder is much more efficient in terms of power consumption without any significant impact on its performance. Index Terms-Reconfigurable video coding, Many-core platform, mapping algorithms

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Section: Simulation Resultsmentioning

confidence: 99%

Power aware mapping of an RVC encoder on a many-core platform

Moghadas

Hashemi

2011

2011 IEEE International Symposium on Broadband Multimedia Systems and Broadcasting (BMSB)

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“…Interactive multimedia applications normally require the use of advanced video codecs, such as the widely used H264/AVC video codec [7]. Implementing the H264/AVC video codec in hand-held devices is a challenge by itself because of the requirements described by Hillestad [6] above, and because custom high performance digital signal processors (DSPs) are needed.…”

Section: Introductionmentioning

confidence: 99%

Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios

Yassin

Catthoor

Kjeldsberg

et al. 2018

Microprocessors and Microsystems

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Many modern applications exhibit dynamic behavior, which can be exploited for reduced energy consumption. We employ a two-phase combined design-time/run-time methodology that identifies different run-time situations and clusters similar behaviors into system scenarios. This methodology is integrated with our framework for system scenario based designs, which dynamically tune the hardware to match the application behavior. We focus on streaming media applications, and achieve significant energy reductions for an extracted control structure of a video codec widely used in hand-held devices today. We encode a video stream consisting of different frame sizes based on measured available wireless bandwidth. Energy consumption is measured with a modified microcontroller board from Atmel with two alternative voltage and frequency settings. While maintaining the perceptual video quality and frame rate, our method results in up to 49% energy reduction for our encoded streams. The average tuning overhead of our mechanism is negligible after applying simple loop transformations to the encoder control structure. We furthermore show how to obtain up to 34.3% energy reductions for a system with limited slack available, by dynamically exploiting the available sleep modes.

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“…The international video coding standard H.264/AVC [1] can produce a perceptually equivalent quality video stream at less than half of the bit rate over a wide range of bit rates and video resolutions compared to previous standards [2], [3]. Due to its superior coding efficiency, it has been adopted in several important applications including video telephony, broadcast, video streaming, HD-DVD, Bluray Disc, and video storage.…”

Section: Introductionmentioning

confidence: 99%

H.264 Deblocking Speed-up Using Hybrid Optimization Technique

Kamal¹

2012

IOSRJECE

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The proposed method defines the problem of reducing the complexity of H.264 decoding. Since deblocking accounts for a significant percentage of H.264 decoding time. Observing that branch operations are costly and that in the deblocking process there are events with significantly high probability of occurrence. The idea of Hybrid optimization to speed up the boundary strength derivation and the true-edge detection by taking advantage of the biased statistical distribution is applied. The proposed techniques can reduce the deblocking computation time, while maintaining the bit-exact output.

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Real-Time Software Implementation of H.264 Baseline Profile Video Encoder for Mobile and Handheld Devices

Cited by 9 publications

References 5 publications

Power aware mapping of an RVC encoder on a many-core platform

Power aware mapping of an RVC encoder on a many-core platform

Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios

H.264 Deblocking Speed-up Using Hybrid Optimization Technique

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