Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios

Yassin, Yahya H.; Catthoor, Francky; Kjeldsberg, Per Gunnar; Perkis, Andrew

doi:10.1016/j.micpro.2017.12.002

“…As we mentioned in Section 1, the system-scenario-based design methodology is a combined design-time and run-time methodology [39] to exploit the application's dynamic behavior at run time, leading to significant optimization potential. According to our simulations, the energy consumption is reduced by combining voltage scaling techniques applied to SRAM cells with the system-scenario-based design method in our framework.…”

Section: System-scenario-based Design Methodologymentioning

confidence: 99%

System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications

Seyedi,

Gunnar Kjeldsberg,

Birkeland

2024

Computer Memory and Data Storage

0

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Cache memory circuits are one of the concerns of computing systems, especially in terms of power consumption, reliability, and high performance. Voltage-scaling techniques can be used to reduce the total power consumption of the caches. However, aggressive voltage scaling significantly increases the probability of memory failure, especially in environments with high radiation levels, such as space. It is, therefore, important to deploy techniques to deal with reliability issues along with voltage scaling. In this chapter, we present a system-scenario methodology for radiation-hardened memory design to keep the reliability during voltage scaling. Although any SRAM array can benefit from the design, we frame our study on the recently proposed radiation-hardened cell, Nwise, which provides high level of tolerance against single event and multi event upsets in memories. To reduce the power consumption while upholding reliability, we leverage the system-scenario-based design methodology to optimize the energy consumption in applications, where system requirements vary dynamically at run time. We demonstrate the use of the methodology with a use case related to satellite systems and solar activity. Our simulations show that we achieve up to 49.3% power consumption saving compared to using a cache design with a fixed nominal power supply level.

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“…In order to estimate the values of C E , I 0 and V 0 , we measure the total power consumption of our SAM4L microcontroller at 40 MHz and 20 MHz with V dd = 1.8 V, and similarly at 12 MHz with V dd = 1.2 V. The measurements were done directly on the SAM4L board using an oscilloscope and ampere meter. Details on a similar experimental setup can be found in [29]. With these three measurements we use Equation 7to find the values of C E , I 0 and V 0 .…”

Section: Estimation Of the Power Consumptionmentioning

confidence: 99%

Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware

Balaji

¹

,

Marty

²

,

Das

³

et al. 2020

J Sign Process Syst

Self Cite

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Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5's system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 pro-

show abstract

“…In order to estimate the values of C E , I 0 and V 0 , we measure the total power consumption of our SAM4L microcontroller at 40 MHz and 20 MHz with V dd = 1.8 V, and similarly at 12 MHz with V dd = 1.2 V. The measurements were done directly on the SAM4L board using an oscilloscope and ampere meter. Details on a similar experimental setup can be found in [29]. With these three measurements we use Eq.…”

Section: Estimation Of the Power Consumptionmentioning

confidence: 99%

Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode

Yassin

¹

,

Jahre

²

,

Kjeldsberg

³

et al. 2020

J Sign Process Syst

Self Cite

3

0

View full text Add to dashboard Cite

Stringent power budgets in battery powered platforms have led to the development of energy saving techniques such as Dynamic Voltage and Frequency scaling (DVFS). For embedded system designers to be able to ripe the benefits of these techniques, support for efficient design space exploration must be available in system level simulators. The advent of the edge computing paradigm, with power constraints in the mW domain, has rendered this even more essential. Without a fast and accurate methodology for architecture simulation and energy estimation, the benefit of new ideas and solutions cannot be evaluated. In this paper, we propose a non-intrusive application controlled DVFS management implementation in the GEM5 simulator, used with GEM5’s system call emulation mode. We also propose a novel architecture independent energy model based on categorization of different measurable workload classes. Our energy model is parametrized and calibrated with power measurements on a SAM4L microcontroller board, containing an ARM Cortex M4 processor. Together with the GEM5 output statistics, the model accurately estimates the total energy consumption of our simulated system. The results from our modified GEM5 simulator are validated with representative signal processing applications. After correction of systematic offset errors, our results deviate with less than 4% compared to measurements from the SAM4L microcontroller. Our contributions in this paper can easily be tailored to other processor models in GEM5 and to future versions of GEM5. It will therefore enable system architects to explore new techniques and compare the improvements relative to existing architectures.

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Techniques for dynamic hardware management of streaming media applications using a framework for system scenarios

Cited by 4 publications

References 26 publications

System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications

System-Scenario Methodology to Design a Highly Reliable Radiation-Hardened Memory for Space Applications

Run-time Mapping of Spiking Neural Networks to Neuromorphic Hardware

Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode

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