Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform

Ding, Dandan; Wang, Silong; Liu, Zoe; Yuan, Qingshu

doi:10.1049/cje.2019.06.020

Cited by 8 publications

(3 citation statements)

References 16 publications

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“…To improve both throughput and hardware resources, ref. [18] proposed a four-stage pipeline architecture. This approach provides a frame rate of 15 FPS with a high bit rate/area (47 Kbps/LUT).…”

Section: Synthesis Resultsmentioning

confidence: 99%

Hardware Architecture for Realtime HEVC Intra Prediction

2023

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Researchers have, in recent times, achieved excellent compression efficiency by implementing a more complicated compression algorithm due to the rapid development of video compression. As a result, the next model of video compression, High-Efficiency Video Coding (HEVC), provides high-quality video output while requiring less bandwidth. However, implementing the intra-prediction technique in HEVC requires significant processing complexity. This research provides a completely pipelined hardware architecture solution capable of real-time compression to minimize computing complexity. All prediction unit sizes of 4×4, 8×8, 16×16, and 32×32, and all planar, angular, and DC modes are supported by the proposed solution. The synthesis results mapped to Xilinx Virtex 7 reveal that our solution can do real-time output with 210 frames per second (FPS) at 1920×1080 resolution, called Full High Definition (FHD), or 52 FPS at 3840×2160 resolution, called 4K, while operating at 232 Mhz maximum frequency.

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Section: Synthesis Resultsmentioning

confidence: 99%

Hardware Architecture for Realtime HEVC Intra Prediction

2023

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“…Ding et al proposed a lexible HEVC intra encoder [36] implemented on an FPGA. The encoder is designed as a conigurable framework of basic processing elements which implement the encoder functionality.…”

Section: Intra-frame Compressionmentioning

confidence: 99%

Image and Video Coding Techniques for Ultra-low Latency

et al. 2022

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The next generation of wireless networks fosters the adoption of latency-critical applications such as XR, connected industry, or autonomous driving. This survey gathers implementation aspects of different image and video coding schemes and discusses their tradeoffs. Standardized video coding technologies such as HEVC or VVC provide a high compression ratio, but their enormous complexity sets the scene for alternative approaches like still image, mezzanine, or texture compression in scenarios with tight resource or latency constraints. Regardless of the coding scheme, we found inter-device memory transfers and the lack of sub-frame coding as limitations of current full-system and software-programmable implementations.

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“…Note that a configurable H.265/HEVC video encoding architecture has been introduced in [19] using FPGA. The proposed H.265/HEVC encoder is structured using four stages coding tree pipelined unit, and targeting a flexible FPGA platform.…”

Section: Introduction and Literature Reviewmentioning

confidence: 99%

Homeland security video surveillance system utilising the internet of video things for smart cities

Ismail

Hammad

Darwich

et al. 2021

IET Computers & Digital Tech

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In the contemporary video surveillance system, there have been many efforts made to maintain high security and extend the coverage areas in most of the countries around the world. The deployment of many surveillance cameras and sensors capable of detecting abnormal and meaningful events on the territories' streets and airports is an aspect of internal security. There are two main problems that affect the homeland security system, and the security cameras and sensors are not enough to cover all areas in the country. This is because of the high cost of the video surveillance cameras and the sensor installations, and the non‐standardisation of security cameras and sensors manufacturing, which is due to the differentiated infrastructure of companies or organizations that provide home security. The authors introduce a design and hardware implementation of a motion estimation (ME) co‐processor that can be used for video surveillance cameras in homeland security. The proposed ME co‐processor, if adopted in video surveillance cameras, can be connected utilising an internet of video things infrastructure (IoVT). The proposed co‐processor is suited for high‐efficiency encoding video surveillance systems (H.265/HEVC). Furthermore, to reduce the memory I/O, data reuse Level A and Level B have been used in the proposed architecture while taking full advantage of the hardware resources. Moreover, an effective local memory has been used to reuse the data during the process of loading both the search area and the current block into the processing element array (PE array). The performance of the proposed architecture has been calculated using subjective and quantitative measures techniques and compared to the full search block‐based motion estimation (FSBB‐ME) algorithm. Moreover, the proposed architecture achieves a very high video resolution accuracy that is similar to the accuracy of the FSBB‐ME algorithm. Modelism‐version10.4a has been used for simulation and time verification testing proposes. The proposed ME co‐processor can be embedded in the compressing decompressing and high definition broadcast for video surveillance systems.

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Real‐Time H.265/HEVC Intra Encoding with a Configurable Architecture on FPGA Platform

Cited by 8 publications

References 16 publications

Hardware Architecture for Realtime HEVC Intra Prediction

Hardware Architecture for Realtime HEVC Intra Prediction

Image and Video Coding Techniques for Ultra-low Latency

Homeland security video surveillance system utilising the internet of video things for smart cities

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