Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach

Kaibou, Redouane; Azzaz, Mohamed Salah; Benssalah, Mustapha; Teguig, Djamal; Hamil, Hocine; Merah, Amira; Akrour, Meriam Tinhinane

doi:10.1007/s11554-021-01073-3

Cited by 18 publications

(2 citation statements)

References 22 publications

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“…To demonstrate the interest of our approach, we have successfully implemented in the FPGA technology the Euler's numerical resolution to resolve 3D continuous non-linear differential equations. The hardware implementation results provide a good trade-off between high security, perfor- Finally, in the light of these results the present TRNG based new multi-wing attractor can be used in cryptographic communications and replace current processing such as in [33,34] as well as in many application fields, especially insecure communication.…”

Section: Discussionmentioning

confidence: 77%

Design and FPGA implementation of TRNG based on a new multi-wing attractor in Lorenz chaotic system

Azzaz

Fellah

Tanougast

et al. 2021

Eur. Phys. J. Spec. Top.

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This paper presents a new way of designing a multi-wing chaotic system. The proposed design is based on 3D continuous chaotic system of Lorenz, improved by introducing a saw-tooth and sine functions. The basic proprieties of the proposed system are analyzed using of equilibrium points, phase portrait, Lyapunov exponent, and bifurcation diagram. Furthermore, the modeling of the design is based on Euler method using hardware description language (VHDL) and validated on Xilinx Virtex-II-Pro FPGA platform. Fixed-point arithmetic coding is employed to represented data on 32 bits (16Q16). Finally, the proposed system used to design a new chaos-based TRNG True Random Number Generators by analyzing its chaotic dynamical behavior and FPGA implementation performances. The proposed hardware architecture is based on two stages of pipeline and parallel structure (only 2 clock cycles). Experimental implementation results demonstrate that the design can achieve a maximum operating frequency of 12.649 MHz and a throughput of 202 Mbit/s. Besides, the random bit sequences produced by TRNG have been successfully passed the NIST-800-22 statistical standards tests. The proposed multi-wing attractor presents also complex dynamics and it can be applied in many engineering applications, especially in embedded cryptographic applications.

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Section: Discussionmentioning

confidence: 77%

Design and FPGA implementation of TRNG based on a new multi-wing attractor in Lorenz chaotic system

Azzaz

Fellah

Tanougast

et al. 2021

Eur. Phys. J. Spec. Top.

Self Cite

View full text Add to dashboard Cite

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“…From a technological standpoint, FPGAs are ideal for processing data in parallel at high speeds. Because of this, they allow for a high level of customization [3]. Their fast processing speeds, ability to be implemented in parallel, and ability to produce deterministic performance and latency make them excellent options for real-time detection algorithm implementation [4][5] [6].…”

Section: Introductionmentioning

confidence: 99%

An FPGA Implementation of Basic Video Processing and Timing Analysis for Real-Time Application

Abdulkhaleq Al-yoonus,

Ahmed Al-kazzaz

2024

IJCDS

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For real-time video processing, the analysis time is a big challenge for researchers. Since digital images from cameras or any image sources can be quite large, it is common practice for researchers to divide these large images into smaller sub-images. The present study proposes a subsystem module to read and display the region of interest (ROI) of real-time video signals for static camera applications to prepare for background subtraction (BGS) algorithm operation. The proposed subsystem was developed using Verilog hardware description language (HDL), synthesized, and implemented in the ZYBO Z7-10 platform. An ROI background image of (360×360) resolution was selected to test the operation of the module in real time. The subsystem consists of five basic modules. Timing analysis was used to determine the real-time performance of the proposed subsystem. Multi-clock domain frequencies are used to manage the module operations, 445.5MHz, 222.75MHz, 148.5MHz, and 74.25MHz, which are six, three, two, and one-time pixel clock frequencies, respectively. These frequencies are chosen to perform five basic processing operations in real-time during the pixel period instant. Two strategies are selected to explain the effectiveness of choosing the trigger instant of the used clock signals on the system performance. The operation revealed that the latency of the proposed ROI reading subsystem was 13.468ns (one-pixel period), which matched the requirements for real-time applications.

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Downsampling in uniformly-spaced windows for coding-based Palmprint recognition

Yang

Leng

Min

2023

Multimed Tools Appl

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Real-time FPGA implementation of a secure chaos-based digital crypto-watermarking system in the DWT domain using co-design approach

Cited by 18 publications

References 22 publications

Design and FPGA implementation of TRNG based on a new multi-wing attractor in Lorenz chaotic system

Design and FPGA implementation of TRNG based on a new multi-wing attractor in Lorenz chaotic system

An FPGA Implementation of Basic Video Processing and Timing Analysis for Real-Time Application

Downsampling in uniformly-spaced windows for coding-based Palmprint recognition

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