An FPGA Implementation of Basic Video Processing and Timing Analysis for Real-Time Application

Abstract

For real-time video processing, the analysis time is a big challenge for researchers. Since digital images from cameras or any image sources can be quite large, it is common practice for researchers to divide these large images into smaller sub-images. The present study proposes a subsystem module to read and display the region of interest (ROI) of real-time video signals for static camera applications to prepare for background subtraction (BGS) algorithm operation. The proposed subsystem was developed using Verilog hardware description language (HDL), synthesized, and implemented in the ZYBO Z7-10 platform. An ROI background image of (360×360) resolution was selected to test the operation of the module in real time. The subsystem consists of five basic modules. Timing analysis was used to determine the real-time performance of the proposed subsystem. Multi-clock domain frequencies are used to manage the module operations, 445.5MHz, 222.75MHz, 148.5MHz, and 74.25MHz, which are six, three, two, and one-time pixel clock frequencies, respectively. These frequencies are chosen to perform five basic processing operations in real-time during the pixel period instant. Two strategies are selected to explain the effectiveness of choosing the trigger instant of the used clock signals on the system performance. The operation revealed that the latency of the proposed ROI reading subsystem was 13.468ns (one-pixel period), which matched the requirements for real-time applications.