Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety

Algredo‐Badillo, Ignacio; Morales-Rosales, Luis Alberto; Hernández-Gracidas, Carlos Arturo; Cruz-Victoria, Juan C.; Bautista, Daniel Pacheco; Morales-Sandoval, Miguel

doi:10.3233/jifs-169997

Cited by 4 publications

(1 citation statement)

References 11 publications

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“…Most algorithms that operate online using data from a single image detect defective pixels by computing statistical variations within a neighborhood centered around each pixel. Although these algorithms frequently run on programmable architectures such as traditional computers and embedded processors, custom hardware architectures can provide higher performance with lower resources and power consumption, which are required for applications such as assisted-driving automobiles [ 20 , 21 , 22 ], surveillance systems [ 23 , 24 , 25 ], and biometric recognition [ 26 , 27 , 28 ], among many others. Numerous researchers have proposed custom hardware devices to perform image processing in real time, which reduces power consumption and increases hardware integration.…”

Section: Introductionmentioning

confidence: 99%

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

López-Portilla

Valenzuela

Zarkesh-Ha

et al. 2023

Sensors

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Images produced by CMOS sensors may contain defective pixels due to noise, manufacturing errors, or device malfunction, which must be detected and corrected at early processing stages in order to produce images that are useful to human users and image-processing or machine-vision algorithms. This paper proposes a defective pixel detection and correction algorithm and its implementation using CMOS analog circuits, which are integrated with the image sensor at the pixel and column levels. During photocurrent integration, the circuit detects defective values in parallel at each pixel using simple arithmetic operations within a neighborhood. At the image-column level, the circuit replaces the defective pixels with the median value of their neighborhood. To validate our approach, we designed a 128×128-pixel imager in a 0.35μm CMOS process, which integrates our defective-pixel detection/correction circuits and processes images at 694 frames per second, according to post-layout simulations. Operating at that frame rate, our proposed algorithm and its CMOS implementation produce better results than current state-of-the-art algorithms: it achieves a Peak Signal to Noise Ratio (PSNR) and Image Enhancement Factor (IEF) of 45 dB and 198.4, respectively, in images with 0.5% random defective pixels, and a PSNR of 44.4 dB and IEF of 194.2, respectively, in images with 1.0% random defective pixels.

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Section: Introductionmentioning

confidence: 99%

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

López-Portilla

Valenzuela

Zarkesh-Ha

et al. 2023

Sensors

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Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference

Nagarajan

Sasikumar

Muralidharan

et al. 2020

IFS

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Approximate computing is a rapidly growing technique to speed up applications with less computational effort while maintaining the accuracy of error-resilient applications such as machine learning and deep learning. Inheritance properties of the machine and deep learning process give freedom for the designer to simplify the circuitry to speed up the computation process at the expense of accuracy of computational results. Fundamental blocks of any computation are adders. In order to optimize it for better performance, 2-bit multi-bit approximate adders (MAPX) are proposed in this work which breaks the lengthy carry chain. In contrast with other approximate larger width adders, instead of using accurate adders for the most significant part, here proposed 2-bit MAPX-1 and MAPX-2 adders are arranged in various ways to compose most and least significant parts. Designed 8-bit and 16-bit adders are evaluated for their performance and error characteristics. Proposed 2-bit MAPX-2 shows better error characteristics whose MED is 0.250 while occupying less area and MAPX-1 consumes less power and delay at the cost of accuracy. Among the extended adders, MAPX 8-bit adder design1 outperforms the best performing APX based 8-bit adder design1. The error performance of it is improved by 14%, 42.1% and 50.4% compared to the existing well-performing APX 8-bit Design1, Design2 and Design3 respectively. Similarly, proposed MAPX 16-bit Design1 exhibits overwhelming performance compared to best performing APX 16-bit Design1, and its error performance is improved by 24.3%, 34.9% and 50.3% compared to APX 16-bit Design1, Design2 and Design3 respectively. In order to evaluate the proposed adder for a real application, extended MAPX 16-bit Design1 is fit in the convolution layer of Low Weights Digit Detector (LWDD) convolutional neural network-based digit classification system. Our modified system accelerates the computation process by 1.25 factors while exhibiting the accuracy of 91% and it best fits error-tolerant real applications. All the adders are synthesized and implemented in the Intel Cyclone IV EP4CE22F17C6N FPGA.

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An automatic assessment of road condition from aerial imagery using modified VGG architecture in faster-RCNN framework

Malini¹,

Priyadharshini²,

Sabeena³

2021

IFS

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To develop a surveillance and detection system for automating the process of road maintenance work which is being carried out by surveying and inspection of roads manually in the current situation. The need of the system lies in the fact that traditional methods are time-consuming, tiresome and require huge workforce. This paper proposes an automation system using Unmanned Aerial Vehicle which monitors and detects the pavement defects like cracks and potholes by processing real-time video footage of Indian highways. The collected data is processed and stored as images in a road defects database which serves as input for the system. The behavior of Region Proposal Network (RPN) is made smooth by varying the number of region proposals utilized in the model. A regularization technique called dropout is used to achieve higher performance in the proposed Faster Region based Convolutional Neural Networks object detection model. The detections are made with 62.3% mean Average Precision @ Intersection over Union (IoU)> = 0.5 for the generation of 300 region proposals which is a good score for object detections. The comparisons between proposed and existing systems shows that the proposed Faster RCNN with modified VGG-16 performs well than the existing variants.

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Real time FPGA-ANN architecture for outdoor obstacle detection focused in road safety

Cited by 4 publications

References 11 publications

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

A CMOS Image Readout Circuit with On-Chip Defective Pixel Detection and Correction

Fixed point multi-bit approximate adder based convolutional neural network accelerator for digit classification inference

An automatic assessment of road condition from aerial imagery using modified VGG architecture in faster-RCNN framework

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