Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis

Fidalgo, André; Alves, Gustavo R.; Ferreira, José Martins

doi:10.1109/dft.2006.51

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…In testability verification work on the equipment you want to check the UUT (unit under test) the BIT or ATE test and diagnostic capability using fault injection method [1]. As technology advances, the previously manual fault injection method can not meet the work requirements, fault injection automatically technique emerged, automatic fault injection equipment has been the focus of research in this field [2] [3].…”

Section: Introductionmentioning

confidence: 99%

The Application of Fault Injection Using Circuit Simulation in Testability Verification

Yuan

Shang

Heng

et al. 2013

AMM

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The fault injection technology is an important aspect in testability verification, because the actual fault injection in equipment can damage itself, so using circuit simulation fault injection method to instead. Research on the simulation method that based on PSPICE, using VC++ software to design a simulated fault injection system, its structure and function to achieve workflow introduced. Finally, taking a circuit for example uses the system to fault injection and analysis to prove the availability and correctness of the system.

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Section: Introductionmentioning

confidence: 99%

The Application of Fault Injection Using Circuit Simulation in Testability Verification

Yuan

Shang

Heng

et al. 2013

AMM

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“…The basic, extended and OCD-FI configurations were described in [4]. The extended scenarios were presented in [5], and the bandwidth aspects were discussed in [6]. The novelty of this paper consists of presenting, for the first time, a comparative analysis of the partial results that correspond to the various OCD configurations, accompanied by an overall discussion concerning their pros and cons.…”

Section: Noveltymentioning

confidence: 99%

A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

Fidalgo¹,

Alves²,

Gericota³

et al. 2008

Proceedings of the 21st Annual Symposium on Integrated Circuits and System Design

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On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

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