A comparative analysis of fault injection methods via enhanced on-chip debug infrastructures

Abstract

On-chip debug (OCD) features are frequently available in modern microprocessors. Their contribution to shorten the time-to-market justifies the industry investment in this area, where a number of competing or complementary proposals are available or under development, e.g. NEXUS, CJTAG, IJTAG. The controllability and observability features provided by OCD infrastructures provide a valuable toolbox that can be used well beyond the debugging arena, improving the return on investment rate by diluting its cost across a wider spectrum of application areas. This paper discusses the use of OCD features for validating fault tolerant architectures, and in particular the efficiency of various fault injection methods provided by enhanced OCD infrastructures. The reference data for our comparative study was captured on a workbench comprising the 32-bit Freescale MPC-565 microprocessor, an iSYSTEM IC3000 debugger (iTracePro version) and the Winidea 2005 debugging package. All enhanced OCD infrastructures were implemented in VHDL and the results were obtained by simulation within the same fault injection environment. The focus of this paper is on the comparative analysis of the experimental results obtained for various OCD configurations and debugging scenarios.

Design of a high performance FPGA based fault injector for real-time safety-critical systems

“…Research in performing fault injections by utilizing Nexus OCD capabilities was generally focused in two different areas: implementing intrusive additional OCD hardware circuitry on the system under test [2,13,14]; and using COTS fault injectors controlled by host computers [14]- [17].…”

“…OCD circuitry allows for access to internal CPU resources by means of software debugging and development tools. These interfaces are increasingly common [2] and can be used to modify registers and memory contents, providing a useful mechanism to inject faults in processors when a circuit description is not available [3], which allows for faults to be injected into commercial safety grade systems.…”

Boosting software fault injection for dependability analysis of real-time embedded applications

“…It consists of adding one or more modules to an existing system part, for instance, a kernel module into an operating system or a fault injection module into a built-in debug and test infrastructure. It is suitable for those hierarchical mission-critical designs whose components are not easily inspectable [Steininger et al 2003;Zenha-Rela et al 2006;Fidalgo et al 2008]; -simulated fault injection, which exploits a model of the embedded system, where faults can be injected while the system is being simulated using, for instance, a Hardware Description Language (HDL) simulator [Jenn et al 1994;Boue et al 1998] or emulated by means of field programmable gate array (FPGA) devices [Antoni et al 2000;Civera et al 2001]. …”