Real-time and low-power processing of 3D direct/inverse discrete cosine transform for low-complexity video codec

Abstract

The 3D discrete cosine transform and its inverse (3D DCT/IDCT) extend the spatial compression properties of conventional 2D DCT to the spatio-temporal coding of 2D videos. The 3D DCT/IDCT transform is particularly suited for embedded systems needing the low-complexity implementation of both video encoder and decoder, such as mobile terminals with video-communication capabilities. This paper addresses the problem of real-time and low-power 3D DCT/IDCT processing by presenting a context-aware fast transform algorithm and a family of VLSI architectures characterized by different levels of parallelism. Implemented in submicron CMOS technology, the proposed hardware macrocells support the real-time processing of main video formats (up to high definition ones with an input rate of tens of Mpixels/s) with different trade-offs between circuit complexity, power consumption and computational throughput. Voltage scaling and adaptive clock-gating strategies are applied to reduce the power consumption versus the state of the art

A new VLSI architecture for 3D-DCT video compression system

“…Fig. 2 shows a common architecture that has been used by previous researchers ( [2], [6], [7], [8], and [9]). We name the common architecture as the baseline architecture.…”

“…Much research has been done to implement 3D-DCT on hardware [2], [6], [7], [8], [9], and [10]. They proposed a straightforward architecture.…”

“…It was made by mapping an algorithm of 3D-DCT into hardware and has a limitation in terms of timing and performance. In [9], the video system avoid multiplication by reading ROM where all ranges of multiplication results are stored based on the same baseline architecture. Instead, it requires a large size of ROM to store all ranges of multiplication results.…”

“…There were parallel architectures to overcome timing and performance deficiencies found in the baseline architecture. Redundant parallel 2D-DCT engines and array-based parallel architecture were deployed in [9] and [10], respectively. Even though those parallel architectures could make higher resolution feasible, it made hardware area bigger than the baseline architecture.…”

“…N, the number of frequency component per each DCT can be set at 4 or 8 which are common, but we set 4 for rapid prototyping which processes 4×4×4 size of cube. We minimize the size of frame memory to O(N 2 (N-1)/4) instead of O(N 3 )+O(N 2 ) taken by the baseline architecture [9]. We also applied the integer transform developed for H.264 to 3D-DCT.…”