2020
DOI: 10.1007/s00034-020-01557-w
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Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length

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“…eir new approach involved replacing the bit shift elements of a variant of the signed DCT transform by zeros, in order to eliminate the bit shift operations. In [13], an efficient hardware implementation was proposed for high-speed vector-radix decimation-in-frequency three-dimensional DCT with an optimum area and power consumption. In [14], a novel algorithm was proposed to determine the minimum number of low-frequency DCT coefficients required for transform and quantization block in high-efficiency video coding.…”
Section: Related Workmentioning
confidence: 99%
“…eir new approach involved replacing the bit shift elements of a variant of the signed DCT transform by zeros, in order to eliminate the bit shift operations. In [13], an efficient hardware implementation was proposed for high-speed vector-radix decimation-in-frequency three-dimensional DCT with an optimum area and power consumption. In [14], a novel algorithm was proposed to determine the minimum number of low-frequency DCT coefficients required for transform and quantization block in high-efficiency video coding.…”
Section: Related Workmentioning
confidence: 99%