Readout of TPC tracking chambers with GEMs and pixel chip

Abstract

Two layers of GEMs and the ATLAS Pixel Chip, FEI3, have been combined and tested as a prototype for Time Projection Chamber (TPC) readout at the International Linear Collider (ILC). The double-layer GEM system amplifies charge with gain sufficient to detect all track ionization. The suitability of three gas mixtures for this application was investigated, and gain measurements are presented. A large sample of cosmic ray tracks was reconstructed in 3D by using the simultaneous timing and 2D spatial information from the pixel chip. The chip provides pixel charge measurement as well as timing. These results demonstrate that a double GEM and pixel combination, with a suitably modified pixel ASIC, could meet the stringent readout requirements of the ILC.

Compact, directional neutron detectors capable of high-resolution nuclear recoil imaging

“…Similarly, there has been a recent claim that keVscale fluorine recoils are significantly longer than predicted by standard simulation tools [41], which if correct, would drastically improve the sensitivity of gas-based directional dark matter detectors. Our previous generation detectors (which we operated at higher gain than the BEAST TPCs) [42] appeared to have high single-electron sensitivity. BEAST TPCs operating at high gain could be used to characterizing the complete ionization distributions from low-energy nuclear recoils and would help clarify such issues.…”

Application of Time Projection Chambers with GEMs and Pixels to WIMP Searches and Fast Neutron Detection

“…Typically the readout of the ionization in the chamber is achieved with a large array of wires on one end which must be both electrically and mechanically stable. As proposed in [2], we are attempting to update the readout of the TPC with a modern scalable solution. We replace the wire array with the ATLAS FE-I3 pixel chip [3].…”

“…Though not discussed here, similar TPCs are being proposed to study beam backgrounds at the Super KEKB accelerator in Japan. The construction of the first generation prototype was led by J. Kadyk at Lawrence Berkeley National Laboratory (LBNL) [2]. This prototype consists of a small drift gap with a drift electrode (consisting of a wire mesh) above and two layers of GEMs and the pixel chip below, Figure 2.…”

“…Cross section of GEM and pixel chip fixture used in the First Generation prototype[2]. Dimensions in mm.…”

“…(a) FE-I3 pixel chip on ATLAS test board. (b) Modified pixel board suitable for use in TPCs[2] ATLAS test board and schematic of modified board for use in TPCs.…”