Read Error Resilient MLC STT-MRAM Based Last Level Cache

Wen, Wen; Zhang, Youtao; Yang, Jun

doi:10.1109/iccd.2017.80

Cited by 7 publications

(1 citation statement)

References 17 publications

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“…Guo et al [142] proposed a dynamic voltage adjustment technique called DOVA and applied the write voltage depending on the criticality of the cacheline to make a tradeoff between performance and reliability of STT-MRAM-based L1 cache. Wen et al [143] focused on the reliability of MLC-based STT-MRAM cache. MLC can achieve high integration density.…”

Section: E Reliability Solutions From the Computer Architecture Persmentioning

confidence: 99%

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

et al. 2021

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| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption. Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings. Moreover, it is predicted that they could be used for DRAM and SRAM replacement. However, they are prone to manufacturing defects and runtime failures as any other type of memory. This article provides an up-to-date and practical coverage of MRAM test and reliability solutions existing in the literature. After some background on existing MRAM technologies, defectiveness and reliability issues are discussed, as well as functional fault models used for MRAM. This article is dedicated to a summarized description of existing test and reliability improvement methods developed Manuscript

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Section: E Reliability Solutions From the Computer Architecture Persmentioning

confidence: 99%