Exploiting In-Memory Data Patterns for Performance Improvement on Crossbar Resistive Memory

Accelerating 3D vertical resistive memories with opportunistic write latency reduction

“…In recent years, there are many studies [22,25,30] on mitigating the write performance degradation in 2D ReRAM crossbars. In [22,23], the data patterns along BLs were exploited to speed up ReRAM crossbar programming. To overcome the sneak current and undesired voltage degradation issues in 2D ReRAM crossbars, a prior study [22] proposed, instead of always conservatively charging all cells a write latency that is guaranteed to successfully switch the worst-case cell, to optimize write latency based on runtime in-memory data patterns.…”

“…Many recent work [2,5,8,12,14,17,18,21] proposed to exploit the feature of analog current aggregation in ReRAM crossbars for accelerating multiply-add calculations between matrices and vectors. In recent work [22,23], a profiling technique for tracking the data patterns along BLs is proposed. In this work, we also exploit the feature of analog current aggregation feature of ReRAM crossbars for data patterns estimation.…”