Reactive ion etching of PECVD silicon nitride in SF6 plasma

Almeida, Flávia Renata de; Yamamoto, Rintaro; Maciel, Homero Santiago

doi:10.1016/0022-3115(93)90311-l

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…It ensures that the thickness of the layer obtained around the pillars can essentially be its deposited thickness, everywhere on the wafer, and independently of the maskset layout used. This scheme consists of the following steps: 1) starting from vertical NW pillars (defined with or without a hard-mask on top), a thin oxide liner and a nitride layer (or other materials, depending on the intended purpose) are deposited on the wafer; 2) a 248nm lithography resist is coated on the wafer; 3) the resist is etched-back isotropically using an O2-based plasma, stopping at a targeted resist thickness (ttarget,resist) in the areas in-between pillars, and with ttarget,resist determined by the etch chemistry selectivity towards resist during the next etch step; 4) an isotropic etch is performed to etch-back the nitride layer (31,32) in areas not covered by resist (using a F-based chemistry) and set its final height or thickness there; 5) the resist is removed by a O2/N2-based strip; and finally 6) the exposed part of the oxide liner can be removed with a short diluted hydrofluoric acid (dHF) or a siconi (33) / dHF process. Examples of SEM images at different stages of this alternative process scheme are shown in Figs.…”

Section: Vertical Nwfet Devices Integrationmentioning

confidence: 99%

(Invited) Vertical Nanowire FET Integration and Device Aspects

Veloso¹,

Altamirano-Sánchez²,

Brus³

et al. 2016

ECS Trans.

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This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

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Section: Vertical Nwfet Devices Integrationmentioning

confidence: 99%

(Invited) Vertical Nanowire FET Integration and Device Aspects

Veloso¹,

Altamirano-Sánchez²,

Brus³

et al. 2016

ECS Trans.

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“…Silicon oxide (SiO x ) and silicon nitride (SiN x ) films have been widely used in various microdevices, such as logic, memory, and microelectromechanical systems devices [1][2][3][4]. Reactive ion etching with fluorocarbon gases and sulfur hexafluoride has been used to pattern SiO x and SiN x thin films in dry atmospheres [5][6][7][8]. Such fluorine (F)-based plasmas can etch SiO x and SiN x at high rates of more than 50 nm min −1 .…”

Section: Introductionmentioning

confidence: 99%

High-rate etching of silicon oxide and nitride using narrow-gap high-pressure (3.3 kPa) hydrogen plasma

Nomura,

Kakiuchi,

Ohmi

2024

J. Phys. D: Appl. Phys.

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We investigated the etching behavior of silicon oxide (SiOx) and silicon nitride (SiNx) in narrow-gap, high-pressure (3.3 kPa) hydrogen (H2) plasma under various etching conditions. Maximum etching rates of 940 and 240 nm/min for SiOx and SiNx, respectively, were obtained by optimizing the H2 gas flow rate. The dependence of the etching rate on gas flow rate implied that effective elimination of etching products is important for achieving high etching rates because it prevents redeposition. The sample surfaces, especially the oxide surfaces, were roughened and contained numerous asperities after etching. Etching rates of both SiOx and SiNx decreased as the temperature was raised. This suggests that atomic H adsorption, rather than H-ion bombardment, is an important step in the etching process. X-ray photoelectron spectroscopy revealed that the etched nitride surface was enriched in silicon (Si), suggesting that the rate-limiting process in high-pressure H2 plasma etching is Si etching rather than nitrogen abstraction. The etching rate of SiOx was three times higher than that of SiNx despite the higher stability of Si–O bonds than Si–N ones. One reason for the etching difference may be the difference between the bond densities of SiOx and SiNx. This study presents a relatively non-toxic, low-cost, and eco-friendly dry etching process for Si-based dielectrics using only H2 gas in comparison with the conventional F-based plasma etching methods.

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“…At the beginning of the discussion on the etching mechanism, the fluorine (F) effect was mainly discussed. [23][24][25][26][27][28][29][30][31] Fluorine can react with both Si and N, making volatile species, such as SiF x and NF x . Later, some researchers pointed out that the NO radical is important for removing SiN and improving selectivity; however, the selectivity to SiO 2 was not high in that case.…”

Section: Introductionmentioning

confidence: 99%

SiN etching characteristics of Ar/CH₃F/O₂ plasma and dependence on SiN film density

Ohtake¹,

Wanifuchi

Sasaki

2016

Jpn. J. Appl. Phys.

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We evaluated the silicon nitride (SiN) etching characteristics of Ar/O2/hydrofluorocarbon plasma. Ar/CH3F/O2 plasma achieved a high etching selectivity of SiN to SiO2 by increasing the oxygen flow rate. We also evaluated the dependence of SiN etching characteristics on SiN film density. A low-density film deposited at a low temperature of 200 °C (by plasma-enhanced CVD, PECVD) showed an 8–20% lower etching rate of SiN than a high-density film deposited at a high temperature of 780 °C (by low-pressure CVD, LPCVD) when we had a low RF bias of 30 W. This PECVD film might move the competitive balance to oxidation from fluorination, reducing the SiN etching rate. However, when we have a high RF bias of more than 50 W, the SiN etching rate is 2–15% higher in the PECVD film than in the LPCVD film. The etching rate of SiN at various densities depends on the balance between oxidation and ion bombardment.

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Reactive ion etching of PECVD silicon nitride in SF6 plasma

Cited by 6 publications

References 5 publications

(Invited) Vertical Nanowire FET Integration and Device Aspects

(Invited) Vertical Nanowire FET Integration and Device Aspects

High-rate etching of silicon oxide and nitride using narrow-gap high-pressure (3.3 kPa) hydrogen plasma

SiN etching characteristics of Ar/CH₃F/O₂ plasma and dependence on SiN film density

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Reactive ion etching of PECVD silicon nitride in SF6 plasma

Cited by 6 publications

References 5 publications

(Invited) Vertical Nanowire FET Integration and Device Aspects

(Invited) Vertical Nanowire FET Integration and Device Aspects

High-rate etching of silicon oxide and nitride using narrow-gap high-pressure (3.3 kPa) hydrogen plasma

SiN etching characteristics of Ar/CH3F/O2 plasma and dependence on SiN film density

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SiN etching characteristics of Ar/CH₃F/O₂ plasma and dependence on SiN film density