RCBus: Row-Column Bus Topology for Optical Network-on-Chip

Abstract

Abstract-Future chip multi-processors (CMPs) will require high-performance yet low-energy networks-on-chip to provide scalable communication for the increasing number of cores. CMOS-compatible nanophotonic interconnects have recently emerged as a promising candidate for replacing traditional electrical network-on-chip, by providing high bandwidth chipwide communication at low latency and power. In this paper, we utilize the emerging nanophotonic technology and propose RCBus, an optical network-on-chip topology in which multiple nanophotonic buses are uniformly distributed in each row and column of a two-dimensional torus network. Each bus employs a dense-wavelength-division-multiplexing optical waveguide to enable high-bandwidth express traversal along each dimension. We use multiple write single-read schemes and virtual channel based token protocol to implement light-speed arbitration and flow control. The optical-electrical interface is also studied in the paper. The proposed optical network-on-chip can exploit the advantages of both photonic bus and direct torus topology. Simulation results under synthetic and real-world application traffic show that RCBus is 2X better in terms of performance than the electrical mesh network-on-chip while saving nearly 30% power, and achieves on average 24 % throughput improvement at much lower cost compared to the state-of-theart optical network.

A Fair Admission Control Mechanism for Efficient Utilization of Resources in On-chip Nanophotonic Crossbars

“…To address the fairness issues, a fair token slot mechanism is presented in [35]. Fu et al [36] employ MWSR token-ring busses of Corona to implement rows and columns of an optical 2D torus, and modified the token-based arbitration scheme so as to support virtual channel flow control.…”

“…This choice of δ follows from our estimate of controller's minimal delay (5.4 ns) obtained from our hardware implementation in Section 8. Moreover, based on (36) and in accordance to our simulated crossbar, we consider 20 waveguides to realize the communication channels between the central controller and the on-chip nodes.…”

Energy-efficient Hybrid Optical-Electronic Network-on-Chip for Future Many-core Processors

“…Thanks to recent progresses in optical device integration, nanophotonic interconnect, which is featured with high bandwidth, low transmission latency and power, has emerged as a promising candidate for future on-chip communication fabric. Recently proposed optical network-on-chip (ONoC) have demonstrated exceptional throughput with low runtime power dissipation [1]- [8]. However, these bus-based ONoCs suffer from great static power consumption, with the main contributors being the laser source and optical-electronic modems [4]- [8].…”