RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory

Zhang, Meng; Wu, Fei; Chen, Xubin; Du, Yajuan; Zhao, Yahui; Wan, Jiguang; Xie, Conghua

doi:10.1109/access.2018.2873081

Cited by 10 publications

(7 citation statements)

References 47 publications

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“…BNU completes the functions of equation ( 3), (4), and (5). CNU executes equation (2) and (3). The check node message can be recovered by equation ( 3) and (4).…”

Section: B Ldpc Decoder Architecturementioning

confidence: 99%

“…NAND Flash is widely used in portable devices such as mobile phone, digital camera and tablet computer for its large storage capacity and low power consumption [1]. However, high-capacity NAND Flash memory, which employs multilevel cell (MLC) technique, suffers higher error rate and lower reliability [2]. Recently, Low-Density Parity-Check (LDPC) coding technique has gained a large attention to reduce the bit error rate of MLC based NAND Flash [3].…”

Section: Introductionmentioning

confidence: 99%

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High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

Zhang

Lian

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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In conventional Low-Density Parity-Check (LDPC) decoders, the real-time processing performance should meet its maximum decoding iterations for all packets and the work frequency or supply voltage is always fixed at a high level, which decreases its energy efficiency. In this paper, an energyefficient LDPC decoding architecture with an adaptive voltagefrequency scaling (AVFS) scheme is presented. According to the usage of input packet FIFO related to variable decoding iterations, the architecture can dynamically adjust decoder's work frequency and supply voltage to reduce the processing energy while meeting its real-time processing requirement. Finally, the decoder is implemented with 28 nm CMOS process. Experimental results show that our decoder has a throughput of 1590 Mb/s when the raw bit error rate (RBER) of Flash memory is up to 10 -2 . The power consumption of the decoder can be reduced by 25%-62% and energy efficiency can be increased to 1.3-2.5 times under different AWGN noise.

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“…BNU completes the functions of equation ( 3), (4), and (5). CNU executes equation (2) and (3). The check node message can be recovered by equation ( 3) and (4).…”

Section: B Ldpc Decoder Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

Zhang

Lian

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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“…Ho et al [ 26 ] proposed a one-shot program design to accelerate programming speed of 3D flash memories and to reduce data error rates. Zhang et al [ 27 ] considered to improve the read performance of 3D SSDs in the view of ECC efficiency and proposed a RBER aware multi-sensing scheme to decrease the number of read thresholds.…”

Section: Background and Related Workmentioning

confidence: 99%

Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance Cliff

Liu

Gao

et al. 2021

Micromachines

Self Cite

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The recent development of 3D flash memories has promoted the widespread application of SSDs in modern storage systems by providing large storage capacity and low cost. Garbage collection (GC) as a time-consuming but necessary operation in flash memories largely affects the performance. In this paper, we perform a comprehensive experimental study on how garbage collection impacts the performance of flash-based SSDs, in the view of performance cliff that closely relates to Quality of Service (QoS). According to the study results using real-world workloads, we first observe that GC occasionally causes response time spikes, which we call the performance cliff problem. Then, we find that 3D SSDs exacerbate the situation by inducing a much higher number of page migrations during GC. To relieve the performance cliff problem, we propose PreGC to assist normal GC. The key idea is to distribute the page migrations into the period before normal GC, thus leading to a reduction in page migrations during the GC period. Comprehensive experiments with real-world workloads have been performed on the SSDsim simulator. Experimental results show that PreGC can efficiently relieve the performance cliff by reducing the tail latency from the 90th to 99.99th percentiles while inducing a little extra write amplification.

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“…[1][2] While the transition from 2D to 3D structures has achieved a huge reduction in device size and bit cost, size scaling is still highly required for further development of 3D NAND flash memory. For instance, 3D charge-trap (CT) NAND flash memory, which usually adopts a macaroni-like vertical channel structure, has been rapidly developed because of its ultra-high storage density, low cost, well reliability, and diversity in novel applications [3][4][5][6][7][8]. The cylindrical shape of 3D CT NAND with ONO stack (SiO2/Si3N4/SiO2) from inside out is beneficial to the field distribution in the CT layer (Si3N4), which allows thicker tunneling oxide (SiO2) to enlarge the memory window.…”

Section: Introductionmentioning

confidence: 99%

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si2N2O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (VN) and interstitial Ti (Tii), can couple with the conduction band of Si2N2O to lead to lateral charge loss. On the other hand, the N substituting Si atom (NSi) and Ti substituting Si atom (TiSi) defects in the transition layer can couple through resonance with the trap centers in Si3N4, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.

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RBER Aware Multi-Sensing for Improving Read Performance of 3D MLC NAND Flash Memory

Cited by 10 publications

References 47 publications

High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory

Observation and Optimization on Garbage Collection of Flash Memories: The View in Performance Cliff

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

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