Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

Blaauw, David; Kalaiselvan, S. A.; Lai, Kuan-Yu; Ma, Wei-Hsiang; Pant, Sanjay; Tokunaga, Carlos; Das, Shidhartha; Bull, David

doi:10.1109/isscc.2008.4523226

Cited by 180 publications

(76 citation statements)

References 4 publications

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“…Razor II [15] is a DVS system that uses a Razor II flip-flop for TED. The (delay-error tolerant) flip-flops from Razor II are placed on all critical paths within a pipeline and are used to scale the supply voltage V dd to the point of first failure (PoFF).…”

Section: Razormentioning

confidence: 99%

“…The power overhead for a Razor II flip-flop compared to standard flip-flop for a 10% activity factor is 28.5%. The overhead is calculated from a 1.2 V, 0.13 µm CMOS circuit [15]. …”

Section: Razormentioning

confidence: 99%

“…The switching energy assuming rail-to-rail swing is: 13) where C ef f is the average effective switched capacitance per operation. The leakage energy is: 15) where T op is the time to complete an operation and L DP is the critical path depth in characteristic inverter delays. The total energy per operation is then expressed as [2]:…”

Section: Energy Consumptionmentioning

confidence: 99%

“…Adding a control voltage to TG3 provides postmanufacturing tuning capability [15] of the PULSE duration. To operate TDTBsubII, tuning was not required during simulation (i.e.…”

Section: Tdtbsubiimentioning

confidence: 99%

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Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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Ajoitusvirheentunnistus (TED) mahdollistaa energian kulutuksen vähentämisen mikroprosessoreissa. Tässä diplomityössä on kaksi versiota ajoitusvirheentunnistavasta salvasta (esim. TDTBsubI ja TDTBsubII) ja systeemitason testipiiri (SystemTest), joka käyttää TDTBsub salpaa, mikä on suunniteltu toimimaan kynnysalueen alapuolella. Diplomityö esittelee ensin dynaamisen jännitteen skaalauksen (DVS), koska TED käytetään sellaisissa järjestelmissä. Seuraavaksi esitellään teoriaa kynnysalueen alapuolen suunnittelun haasteista. Sitten esitellään molempien TDTBsub salpojen ja SystemTest-lohkojen suunnittelu. Simulaatiotuloksia esitellään keskittyen operaatiotaajuuteen, energian kulutukseen ja toimintavarmuuteen variaatiot huomioon ottaen. Operoitaessa kynnysalueen alapuolella TDTB-piirillä keskityttiin koon mitoittamiseen ja suunnittelutyyliin. Ennen kaikkea kaikkien komponenttien mitoituksen piti olla suurempi kuin minimi CMOS-tekniikan leveydet. Vaikka mitoittamisella saavutettiin toimintavarmuutta kynnysalueen alapuolella toimittaessa myös energian kulutus kasvoi siellä toimittaessa. Perinteisiä vuotovirtojen vähentäviä mitoitustoimenpiteitä tehtiin suurimmalle osalle komponenteista. Logiikkatyyli on tärkeää kynnysalueen alapuolella operoitaessa. TDTBsubII salvassa uuden tekniikan näytetään antavan systeemitason suorituskykyä. Simulaatioilla näytettiin kuinka ajoitusvirheentunnistus kykeni toimimaan kynnystason alapuolella. TDTBsubI:n ja yhteenlaskun testipiirin piirinkuvio tehtiin 65nm CMOS-prosessilla. TDTBsubII salpaa ei tehty, koska se suunniteltiin piirin määräajan jälkeen. Piiriä tarkasteltaessa osoittautui, että piiri ei toiminut. Piirin toimimattomuus johtui tuotantovaiheessa tapahtuneesta virheestä eikä suunnittelusta. Avainsanat:sub-threshold,weak inversion,low power,low voltage,digital CMOS To operate TDTBsub into sub-threshold, attention was given to sizing and logic style. In general, the sizing of all components was required to be larger than the minimum CMOS width. Although this provided robustness in sub-threshold, the energy consumption in above sub-threshold was much higher. General leakage reduction sizing techniques were also applied to the majority of components. The choice of logic style is important for sub-threshold operation. In the TDTBsubII latch, a new technique is shown to provide system-level capability. Simulations displayed the capability of TED in sub-threshold. The layout of TDTBsubI and an adder test circuit were constructed in 65 nm CMOS. The TDTBsubII latch was not built since it was designed after the chip deadline. Upon inspection of the chip, it was determined to be inoperative. This mistake was a result of the manufacturering process and not the design in this work. Keywords:sub-threshold, weak inversion, low power, low voltage, digital CMOS ii ForewordThe work for this thesis was carried out at the Electronic Circuit Design Laboratory (ECDL) of TKK. The financial support of this project was provided by the Academy of Finland. The project was coordinated with University of Turku ...

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Section: Razormentioning

confidence: 99%

“…The power overhead for a Razor II flip-flop compared to standard flip-flop for a 10% activity factor is 28.5%. The overhead is calculated from a 1.2 V, 0.13 µm CMOS circuit [15]. …”

Section: Razormentioning

confidence: 99%

Section: Energy Consumptionmentioning

confidence: 99%

“…Adding a control voltage to TG3 provides postmanufacturing tuning capability [15] of the PULSE duration. To operate TDTBsubII, tuning was not required during simulation (i.e.…”

Section: Tdtbsubiimentioning

confidence: 99%

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Sub-threshold operation of a timing error detection latch

Turnquist¹,

Koskinen²

2009

2009 Ph.D. Research in Microelectronics and Electronics

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“…Statistical timing approaches such as those described in [9] and [11] are essential for future micro-power systems. Variation-tolerant architectures will play an important role by allowing detection and correction of transient errors during run-time [12].…”

Section: A Variation-aware Logic Designmentioning

confidence: 99%

Next generation micro-power systems

Chandrakasan

Daly

Kwong

et al. 2008

2008 IEEE Symposium on VLSI Circuits

121

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Emerging microsystems such as portable and implantable medical electronics, wireless microsensors and next-generation portable multimedia devices demand a dramatic reduction in energy consumption. The ultimate goal is to power these devices using energy harvesting techniques such as vibration-to-electric conversion or through wireless power transmission. A major opportunity to reduce the energy consumption of digital circuits is to scale supply voltages to 0.5V and below. The challenges associated with ultra-low-voltage design will be presented. These include variation-aware design for logic and SRAM circuits, efficient DC-DC converters for ultra-low-voltage delivery, and algorithm structuring to support extreme parallelism. This paper also addresses micro-power analog and RF circuits, which require the use of applicationspecific structures and highly digital variation-aware architectures.

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Ultra‐Low‐Power Signal Processing in Autonomous Systems

Piguet

2012

Energy Autonomous Micro and Nano Systems

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Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance

Cited by 180 publications

References 4 publications

Sub-threshold operation of a timing error detection latch

Sub-threshold operation of a timing error detection latch

Next generation micro-power systems

Ultra‐Low‐Power Signal Processing in Autonomous Systems

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