Razor: circuit-level correction of timing errors for low-power operation

Ernst, Daniel; Das, Shidhartha; Lee, S.; Blaauw, David; Austin, Todd; Mudge, Trevor; Kim, Nam Sung; Flautner, Krisztián

doi:10.1109/mm.2004.85

Cited by 333 publications

(222 citation statements)

References 9 publications

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“…Another body of work explored detecting and mitigating errors via circuit techniques [1] [2]. The research using Razor systems assumed that errors will occur and inserts redundancy in latches.…”

Section: Previous Workmentioning

confidence: 99%

Performance boosting under reliability and power constraints

John¹,

Paul²,

Manne³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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We then examine the impact of FP throttling and guardband reduction on the SPEC CPU2006 benchmarks and show that some benchmarks benefit from the frequency improvements with FP throttling while others suffer due to reduced FP throughput.Finally, we present two techniques to determine dynamically when to trade FP throughput for reduced voltage margin and increased frequency, and show performance improvements of up to 15% for CINT2006 benchmarks and up to 8% for CFP2006 benchmarks. Our studies are done on hardware in which FP units generate the worst-case voltage droop. The technique can be modified for architectures in which other units cause the worst droop.

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Section: Previous Workmentioning

confidence: 99%

Performance boosting under reliability and power constraints

John¹,

Paul²,

Manne³

et al. 2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Considering the dominance of transient faults among all fault types in computing systems [5,7,17], we focus on transient faults in this paper. We assume that the fault interarrival rate follows the Poisson distribution [19].…”

Section: Fault Model and Problem Descriptionmentioning

confidence: 99%

“…Moreover, as a traditional design metric, the reliability concerns triggered by increased transient fault rates have become prominent with the continued scaling of CMOS technologies and reduced design margins [5]. In general, energy management schemes exploit available system slack and operate system components at lower performance states, whenever possible, to save energy consumption.…”

Section: Introductionmentioning

confidence: 99%

Priority-monotonic energy management for real-time systems with reliability requirements

Zhu

Aydın

2007

2007 25th International Conference on Computer Design

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“…The in-situ error detection and correction (EDAC) techniques [4,5,6,7,8,9,10,11,12,13] are proposed to eliminate the timing margins. They monitor timing violations by specially designed circuits, and then take measures to recover functionality of the design if such a violation occurs.…”

Section: Introductionmentioning

confidence: 99%

Light-weight one-cycle timing error correction based on hardware software co-design

Ding

Yan

et al. 2016

IEICE Electron. Express

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A light-weight one-cycle EDAC (timing error detection and correction) technique is proposed to eliminate timing margins resulting from process, voltage, temperature and aging (PVTA) variations. The collaborative approach applies TEDPI (timing error deletion programming interface) to pre-detect most of the errors through an offline error prediction model, and pre-correct them at compilation time by using a specially designed error avoidance instruction. Experimental results based on a three-stage commercial processor show that TEDPI has improved peak performance of the traditional EDAC system by 15.6% and reduced the energy consumption by 4.4% with less than 0.71% area overhead.

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Razor: circuit-level correction of timing errors for low-power operation

Cited by 333 publications

References 9 publications

Performance boosting under reliability and power constraints

Performance boosting under reliability and power constraints

Priority-monotonic energy management for real-time systems with reliability requirements

Light-weight one-cycle timing error correction based on hardware software co-design

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